PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 43

• Manufacturer Part Number: PRIXP425BC 869083
• Manufacturer: Intel

Specifications of PRIXP425BC 869083

• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Intel
Table 12.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
UTOPIA Level 2 Interface (Sheet 2 of 2)
UTP_IP_FCI
UTP_IP_SOC
UTP_IP_DATA[7:0]
UTP_IP_ADDR[4:0]
UTP_IP_FCO
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Reset
Post
VI
VI
VI
VI
Z
Type
I/O
O
Table 5 on page
I
I
I
†
UTOPIA Input Data flow control input signal. Also known
as RXEMPTY/CLAV.
Used to inform the processor of the ability of each polled
PHY to send a complete cell. For cell-level flow control in
an MPHY environment, RxClav is an active high tri-
stateable signal from the MPHY to ATM layer. The
UTP_IP_FCI, which is connected to multiple MPHY devices,
will see logic high generated by the PHY, one clock after
the given PHY address is asserted, when a full cell can be
received by the PHY. The UTP_IP_FCI will see a logic low
generated by the PHY, one clock cycle after the PHY
address is asserted if a full cell cannot be received by the
PHY.
In SPHY mode, this signal is used to indicate to the
processor that the PHY has an octet or cell available to be
transferred to the processor.
Should be pulled high
not being utilized in the system.
Start of Cell. RX_SOC
Active-high signal that is asserted when UTP_IP_DATA
contains the first valid byte of a transmitted cell.
Should be pulled high
not being utilized in the system.
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM
UTOPIA-Level-2-compliant PHY.
Should be pulled high
not being utilized in the system.
Receive PHY address bus.
Used by the processor when operating in MPHY mode to
poll and select a single PHY at any one given time.
UTOPIA Input Data Flow Control Output signal: Also
known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the
PHY that the processor is ready to accept data.
In MPHY configurations, UTP_IP_FCO is used to select
which PHY will drive the UTP_RX_DATA and UTP_RX_SOC
signals. The PHY is selected by placing the PHY’s address
on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1
during the current clock, followed by the UTP_OP_FCO
going to a logic 0 on the next clock cycle.
33.
††
††
††
Description
through a 10-KΩ resistor when
through a 10-KΩ resistor when
through a 10-KΩ resistor when
Datasheet
43