PRIXP420ABC 885160 Intel, PRIXP420ABC 885160 Datasheet - Page 32

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PRIXP420ABC 885160

Manufacturer Part Number
PRIXP420ABC 885160
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP420ABC 885160

Lead Free Status / Rohs Status
Compliant
Figure 9.
3.4
Intel
Hardware Design Guidelines
32
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Console UART Interface
MII Interface
The IXP42X product line and IXC1100 control plane processors have two integrated 10/
100-Mbps MAC with two industry-standard Media Independent Interfaces (MII), except
for the IXP422, which has only one MII. The processors include a single Management
Data Interface – Management Data Input Output (MDIO) and Management Data Clock
(MDC). The MII interfaces and the single management data interface are used to
communicate, control, and configure PHY devices.
Figure 10
processors’ MII port. Rates of 25 MHz for 100-Mbps operation or 2.5 MHz 10-Mbps
operation clocks for TX and RX MII interface (ETH_TX_CLK, ETH_RX_CLK) for each
Ethernet PHY are expected to be supplied from onboard oscillators or PLL.
General LAN routing guidelines can be found in
Considerations” on page
Specification.
Control Plane
Product Line
and IXC1100
Processors
IXP42X
UART_RXDATA1
UART_TXDATA1
Intel
Intel
UART_CTS_N1
UART_RTS_N1
illustrates how to interface an IEEE 802.3 standard Ethernet PHY to the
®
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
66. For more detailed information, see the IEEE 802.3
Transceiver
RS-232
Section 6.3.2, “LAN Signal
Document Number: 252817-008US
Connector
6
7
8
9
Considerations
December 2007
DB9
2
3
4
5
1
B2253 -02

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