RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 12

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RPIXP2850BB

Manufacturer Part Number
RPIXP2850BB
Description
Manufacturer
Intel
Datasheet

Specifications of RPIXP2850BB

Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
IXP28XX Network Processor
Introduction
Table 1.
12
Product Features of IXP28XX Network Processors
Sixteen integrated Microengines
(Version 2)
Integrated Intel XScale® core
Two integrated Cryptographic
units (Intel® IXP2850 Network
Processor only)
Three industry-standard RDRAM
interfaces
Four industry-standard 32-bit
QDR SRAM interfaces
Integrated Media Switch Fabric
interface
Industry-standard PCI Bus
Additional integrated features
1356 Ball FCBGA package
Feature
• Operating frequency of up to 1.4 GHz
• Configurable to four or eight threads per Microengine
• 640 Dwords of local memory per Microengine
• Sixteen-entry CAM per Microengine, with single cycle lookup
• Next Neighbor bus accessing adjacent Microengines
• CRC unit per Microengine
• 8K instructions control store per Microengine
• Support for Generalized Thread Signaling
• Operating frequency of up to 700 MHz
• High performance, low power 32-bit embedded RISC processor
• 32-Kbyte instruction cache
• 32-Kbyte data cache
• Operating frequency of 700 MHz
• Support for DES, 3DES, AES, and SHA-1 algorithms
• Support for AES 128-, 192-, and 256-bit keys
• Peak bandwidth of 2.1 Gbytes/sec
• 800-MHz and 1066-MHz RDRAM
• Error Correction Code (ECC)
• Addressable from Intel XScale
• Peak bandwidth of 1.9 Gbytes/sec per channel
• 233-MHz SRAM
• Hardware support for Linked List and Ring operations
• Atomic bit operations
• Atomic arithmetic support
• Addressable from Intel XScale
• Two unidirectional 16-bit Low-Voltage Differential Signaling (LVDS)
• Up to 500 MHz per channel
• Separately configurable for either SPI-4 or CSIX protocols
• PCI Local Bus Specification, Version 2.2* interface for 64-bit, 66-MHz
• Hardware Hash Unit (48-, 64-, and 128-bit)
• 16-KByte Scratchpad Memory
• Serial UART port for debug
• Eight general-purpose I/O pins
• Four 32-bit timers
• Dimensions of 37.5mm x 37.5mm
• 1 mm solder ball pitch
data interfaces
I/O
Description
®
®
core, Microengines, and PCI
core, Microengines, and PCI
Hardware Design Guide

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