RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 134

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IXP28XX Network Processor
Slowport
7.1.2.1
7.1.2.1.1
Example 1.
134
Note: Timing diagrams for all supported modes are provided in the Slowport unit section of the Intel®
Flash PROM Interface Logic
The following sections describe the address latch logic and provide example implementations of
this logic.
Address Latch Logic
The flash memory interface only supports 8-bit devices; therefore, no data packing or unpacking is
required. Since the address bus is only eight bits wide, the 24-bit address must be latched by the
external logic. The address is shifted out by the network processor, eight bits at a time in three
consecutive clock cycles to form the upper 24 bits (A[25:2]) of the address, while the lower two
bits (A[1:0]) are provided on dedicated pins.
The external logic monitors the SP_ALE_L signal; when this signal is asserted, the external logic
latches the presented address on the SP_AD[7:0] bus on the rising edge of SP_CLK for three
consecutive cycles. The least significant byte (LSB) of the address is delivered first and the most
significant byte (MSB) is presented last.
IXP2800 Network Processor Hardware Reference Manual. We recommend that you consult the
HRM and review all of the timing diagrams in that section.
The Verilog* code in
PROM Address Latch Logic
// implementation of address packing logic
always @(posedge sp_clk) begin
end // always @ (posedge sp_clk)
This logic is equivalent to the F377 devices shown in
No additional logic is required to interface to the flash.
for a single write and read transaction, respectively, to the flash memory interface.
if (~rst_l) begin
end
else begin
end // else: !if(~rst_l)
latched_add
sp_ale_l_d
if (~sp_ale_l) begin
end
latched_add[7:0]
latched_add[15:8]
latched_add[23:16] <= latched_add[15:8];
Example 1
<= 24'h000000;
<= sp_ale_l;
depicts an example implementation of the logic:
<= sp_ad_in;
<= latched_add[7:0];
Figure
Figure 82
81.
and
Figure 83
Hardware Design Guide
depict the timing