RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 14

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IXP28XX Network Processor
Introduction
1.2.1
Table 2.
1.2.2
Table 3.
14
Typographical Conventions
This guide contains the following text and typography conventions:
Guide Conventions
Acronyms and Terminology
Table 3
Acronyms and Terminology (Sheet 1 of 3)
AES
ATM
BGA
BWE
CFM
CFMN
Clamshelling
cPCI
CPIX
CSIX
CPLD
CSR
CTM
CTMN
DDR
DES
DLL
DMA
DRAM
Acronym/Terminology
monospace bold
table of contents
table of figures
table of tables
monospace
Convention
defines the acronyms and terminology that are used throughout this document.
Italics
bold
>
New terms and titles of documents or help systems appear in italics.
Special text for labels of items appears in bold type.
Code and names of drives, pathnames, directories, and filenames appear in
Courier monospace type.
Example commands given to show user input.
Each item in the tables of contents, figures, and tables is a hyperlink.
Indicates the sequential choice of menu items. For example, the menu items for
the Developers Workbench are Start > IXA SDK 4.1 > DevWorkbench.
Advanced Encryption Standard
Asynchronous Transfer Mode
ball grid array
Byte Write Enable, a type of control signal that is active low
Clock-to-Master, positive polarity
Clock-to-Master, negative polarity
Locating two devices on opposite sides of the printed circuit board
Compact PCI, a 32- or 64-bit bus, operating at either 33 or 66 MHz
Common Programming Interface Forum
Common Switch Interface
Complex Programmable Logic Device
Control Status Register
Clock-to-Master, positive polarity
Clock-to-Master, negative polarity
Double Data Rate
Data Encryption Standard
Dynamic Link Library
Direct Memory Access
Dynamic Random Access Memory
Description
Definition
Hardware Design Guide