RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 141

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 86.
Example 4.
Hardware Design Guide
Figure 86
Slowport Mode 3 write example showing TXE +1 delay using SP_TXE
The Verilog* code in
32-bit Write Data Packing Logic Implementation
//implementation of latch control for 32-bit pack/unpacking to/from NP
//to uP port
always @(posedge sp_a[0]) begin
//data is shifted during four cycles
//here we can latch all the read data, the controller will
//pulse SPA[0] multiple times but it's a “don't care”
//as we capture all 32-bits on each edge of SP_CP
end // always @ (posedge spa[0])
In the
the read data, decreasing the number of gates needed for implementing the glue logic. If desired,
separate registers for latching the write and read data can be used; in this case, the rising edge of the
SP_RD_L signal is used to capture the read data and the SP_CP signal is not used.
if (~rst_l) begin
end
if (~sp_oe_l && sp_a[1]) begin
end
else begin
end // else: !if(~sp_oe_l && sp_rd_l)
SP_CS[1:0]
SP_AD[7:0]
Example 4
CPP_CLK
SP_ACK
SP_CLK
SP_ALE
SP_DIR
SP_WR
data[31:0]
data[31:24]
data[23:16]
data[15:8]
data[7:0]
if (~sp_rd_l) begin
end
SP_CP
SP_OE
SP_RD
is a Slowport Mode 3 Write example with TXE +1 delay using SP_TXE.
data[31:0]
d8
1
1
1
1
3
1
0
0
1
1
1
code, the 32-bit register used for latching the write data is also used for latching
2
Example 4
3
<= 32'h0000_0000;
4
<= sp_ad_in;
<= data[31:24];
<= data[23:16];
<= data[15:8];
5
<= uP_rd_data;
6
is an example implementation of the logic.
7
d8
8
Rise of SP_CP
9
10
11
12
13
TXE+1 delay
14
15
Rise of SP_CLK
3
16
Internal bus clock
17
18
IXP28XX Network Processor
19
20
TXE in this run is 1 and delays
the change in data by
TXE+1 internal bus clocks
21
22
7d
23 24
25
26
27
Slowport
28
B3924-02
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