RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 143

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

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Figure 88.
Hardware Design Guide
Note: The SHIFT_EN signal is used in combination with a two-bit counter, PACK_CNT, which is used to
Note: The SP_CP signal may pulse after the SP_RD_L signal has been deasserted; therefore, only the
Slowport Mode 3 read example showing RXE = 2
The glue logic latches all 32 bits of read data on the rising edge of SP_CP if SP_RD_L is asserted.
The logic latches all the data on each rising edge and will always get the last 32 bits of data
presented on the data bus, and is therefore unaffected by multiple pulses of the bus. Alternately, the
rising edge of the SP_RD_L signal could be used in place of SP_CP to latch the read data; however
this procedure requires separate registers for the read and write data, as explained in
Section
The read-latching logic, shown in
the same 32-bit register. After the data is captured, the logic must also unpack the data back to the
IXP28XX network processor at eight bits per transfer (MSB to LSB) onto the SP_AD. This is
accomplished by the glue logic driving the first byte of the read data back to the network processor
on the SP_RD_OUT bus when the signal SHIFT_EN is asserted.
steer the appropriate byte, based on the count, onto the SP_RD_OUT bus. The PACK_CNT
counter is incremented on every rising edge of SP_CP if the SHIFT_EN control signal is asserted;
PACK_CNT is cleared if SHIFT_EN is de-asserted. This procedure ensures that PACK_CNT will
be zero at the beginning of each read cycle. As the count increments, the appropriate byte is driven
onto the SP_RD_OUT bus as SP_CP is pulsed to complete the 32-bit transfer.
The SHIFT_EN control signal detects if the SP_OE_L signal is asserted, the SP_RD_L signal is
de-asserted, and the SP_DIR signal is de-asserted; these conditions indicate this is a read cycle and
that the glue logic owns the bus. Ultimately, the SP_RD_OUT bus connects to the output port of a
bidirectional buffer, which will connect to the SP_AD bus. The output enable for this buffer can be
controlled by SP_DIR or the SHIFT_EN control signal. The Verilog* code in
example implementation of the SHIFT_EN control signal and the data unpacking logic.
SP_OE_L, SP_DIR, and SP_CP signals should be used to control the unpacking of the data.
SP_CS[1:0]
SP_AD[7:0]
CPP_CLK
7.1.2.2.4.
SP_ACK
SP_CLK
SP_ALE
SP_DIR
SP_WR
SP_OE
SP_RD
SP_CP
d8
1
1
1
1
3
1
0
0
1
1
1
2
3
4
5
Internal bus clock
6
d8
7
Example
8
Rise of SP_CP
9
10
Data is latched RXE internal
clock cycles before
rising edge of SP_CLK
4, is combined with the data-packing logic and shares
11
12
RXE = 2
13
14
15
Rise of SP_CLK
3
16
17
18
IXP28XX Network Processor
19
20
21
22
7d
23 24
Example 5
25
26
27
Slowport
depicts an
28
Bxxxx
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