RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 144

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IXP28XX Network Processor
Slowport
Example 5.
144
On the clock cycle after the read signal is de-asserted from the downstream device, the glue logic
will drive the first byte of data onto the SP_AD bus since the IXP28XX network processor does not
pulse the SP_CP signal to promote the first read. The remaining three bytes of data are shifted out
on the rising edge of the SP_CP signal to complete the 32-bit transfer.
32-bit Read Unpacking Logic Implementation
// control logic for shifting the 32-bit read data back to IXP, 8-bits
// per cycle
assign shift_en = (~sp_oe_l && ~sp_a[1]);
The following Verilog* code depicts an example implementation of the data unpacking logic:
// implementation of pack_cnt control logic, the count is incremented on each
// rising edge of sp_a[0] if shift_en is active
always @(posedge sp_a[0]) begin
end // always @ (posedge sp_clk)
// Implementation of read data mux, pack_cnt is used to determine which byte
// should be driven onto the sp_rd_out bus
always @ (pack_cnt) begin
end
if (~rst_l) begin
end
else begin
end // else: !if(~rst_l)
//data is shifted during four consecutive cycles
case (pack_cnt)
endcase // case(pack_cnt)
pack_cnt
if (shift_en)begin
end
else if (~shift_en) begin
end
2'b00:
2'b01:
2'b10:
2'b11:
pack_cnt
pack_cnt
sp_rd_out
sp_rd_out
sp_rd_out
sp_rd_out
<= 2'b00;
<= pack_cnt + 1;
<= 2'b00;
//synopsis full_case parallel_case
<= #1 data[31:24];
<= #1 data[23:16];
<= #1 data[15:8];
<= #1 data[7:0];
Hardware Design Guide