RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 54

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IXP28XX Network Processor
QDR SRAM
4.2
Figure 21.
4.2.1
54
Note: All of the SRAMs on a given channel must be the same size.
significant changes in results or may lead to non-working design altogether. That is why it is
strongly recommended that developers thoroughly simulate any new designs or modifications
before committing to any new modifications.
QDR Clocking Scheme
The controller drives out a pair of K clocks (K and K#), and a pair of C clocks (C and C#). The C
and C# clocks externally return to the controller for reading data.
diagram of the clocking scheme for a QDR interface driving four SRAM chips.
Clocking Scheme for a QDR Interface Driving Four SRAMs
SRAM Controller Configurations
Each channel has enough address pins (24) to support up to 64 Mbytes of SRAM. The SRAM
controllers can directly generate multiple port enables (up to four pairs) to allow for depth
expansion; two pairs of pins are dedicated for port-enables. Smaller RAMs use fewer address
signals than the number provided to accommodate the largest RAMs, so some address pins – 23:20
– are configurable as either address or port-enable, based on the control status register (CSR)
setting, as shown in
Intel®
IXP2800
Network
Processor
Table
C0IN/C0IN#
C1IN/C1IN#
C0/C0#
C1/C1#
Termination
K0/K0#
K1/K1#
Termination
14.
Clam-shelled SRAMS
K/K#
K/K#
C0/C0#
C1/C1#
Figure 21
C/C#
C/C#
Hardware Design Guide
Package Balls
Package Balls
shows the clock
A9234-03