RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 73

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 35.
Table 26.
4.5.5.1
Hardware Design Guide
QDR K and K# Signal Trace Width/Spacing Routing
Table 26
QDR K-Clock Stack-up Signal Cross-section Details
Relationship between Address, Control, Data-OUT and K-Clock
The trace lengths of all members the K-Clocks net group should be matched to each other to within
±10 mils. The K-Clock is used to sample Address, CONTROL, and Data-OUT simultaneously.
The K-Clock has only two SRAM loads with no stubs (point-to-point topology). The Data-OUT
has two SRAM loads. However, it has either one long stub between the two SRAMs in case of
daisy chain configuration, or two shorter stubs in case of a T-Topology configuration. The Address
signal has 4 SRAM loads in a T-Topology configuration. The CONTROL signals are similar in
topology to the Data-OUT signal.
Because these signals have different topology and/or different number of loads, the flight time of
each would be different. However, the K-Clock must be used to sample the Data-OUT,
CONTROL, and Address at the same time. Therefore it becomes necessary to match their flight
times with respect to each other. Matching their flight times means adjusting their trace lengths
with respect to each accordingly. If the trace length of on of these three signals is fixed the
individual trace length of each one of the other signals must be controlled according to the
following K-Clk to Data-Out relationship formula:
Similarly, the following formula applies for the K-Clk/Address relationship:
Parameter
Value
T
signal
lists the QDR K-Clock stack-up signal cross-section details.
T
T
d2
d1
Signal
Clock
QDR
K-
Signals
Other
K-Clk-Pkg-trace-length + K-Clk-trunk-length =
K-Clk-Pkg-trace-length + K-Clk-trunk-length =
Width (W)
[mils]
Trace
5
D-Pkg-trace-length + D-trunk-length + 500 mil
Address-Pkg-trace-length + Address-trunk-length + 900 mil
Thickness
(Tsignal)
20 mil or larger
[mils]
Trace
0.5
Prepreg
POWER or GND Plane
POWER or GND Plane
(S) [mils]
Spacing
20 - 25
Trace
Thickness
K, C Clk
[mils]
(TD1)
Signal
D1
5.0
W
Thickness
IXP28XX Network Processor
[mils]
(Td2)
5.7
D2
S
Er(D1) Er(D2)
3.5
K, C Clk
Signal
W
3.8
QDR SRAM
D2
D1
between
Spacing
3994-01
groups
20 - 25
signal
[mils]
73