RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 88

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RPIXP2850BB

Manufacturer Part Number
RPIXP2850BB
Description
Manufacturer
Intel
Datasheet

Specifications of RPIXP2850BB

Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
IXP28XX Network Processor
QDR SRAM
88
Note: This length can be used as a starting point for layout; however, the final overall length values
two, in which case the average should be used. Further, the Q data total length is the average of all
Q lengths, so Q Length = avg(eL6 + L5 + L4). The Q length should not be allowed to vary by more
than ±0.10 inches.
The basic method for determining the length of the loopback clock is C Length + Q Length +
Capacitive Load Delta C&Q. The maximum length in any case cannot be more than one bit-time.
This must then be further constrained to allow for PVT variations; hence, at 200 MHz or for a bit-
time of 2.5 ns, the total flight time delay must not exceed 2.0 ns, i.e., (2.5 ns bit-time – 500ps PVT).
The effective internal package length of the IXP28XX network processor can be calculated. The
propagation delay in the network processor package is approximately 154 ps/inch. The propagation
delay on a PCB can be calculated as 84.735 * Square Root (Er) where Er is the Dielectric
Permittivity of the substrate. For FR4 epoxy glass at 250 MHz, the delay calculation is
approximately 4.2, meaning that the propagation delay of a generic PCB is approximately 174
ps/inch. Consult your PCB vendor for the recommended Er at a specific frequency. Knowing this,
eL can be calculated in inches. The IXP28XX network processor internal package length is given
in µm and the conversion is inches = µm/1000/25.4. Hence:
Now that we know how to calculate lengths, we need to discuss the Capacitive Load Delta term.
Since C[0] and Q lines have more capacitance loading than C[1] (loopclock), C[0] and Q slew rates
are slower with respect to C[1]. The capacitance per pin for a Micron QDRII SRAM is 5 pF
(minimum) to 6 pF (maximum), and the capacitance for an IXP28XX network processor input pin
is 5 pF (minimum) to 10 pF (maximum). Therefore, the total capacitive load at the end of the line
on C[0] is two SRAMs for 10 pF (minimum) and 12 pF (maximum). The total capacitive load at
the end of the line on Q is one IXP28XX network processor for 5 pF (minimum) and 10 pF
(maximum). The total capacitive load at the end of the line on C[1] is one IXP28XX network
processor for 5 pF (minimum) and 10 pF (maximum). C[0] + Q load is therefore 15 pF minimum,
and 22 pF maximum.
The boundary condition deltas (minimum and maximum differences between C[0]+Q – C[1]) are
12 pF (maximum) and 10 pF (minimum). To center the error, select the mean case of 11 pF
Capacitive Load Delta C&Q. This delta in capacitance load can be converted to an effective length.
It is generally accepted that for a transmission line, Co = Td/Zo where Td was calculated above at
174 ps/inch and Zo is 50 Ω — so the intrinsic capacitance Co = 3.48 pF/inch. Then, the delta load
of 11 pF translates into 3.1 extra inches of etch for Capacitive Load Delta C. Effectively, the
difference in capacitance is translated into an additional three inches of trace length that must be
accounted for in the overall loopclock length. This is a very important consideration.
If the user is using a similar PCB dielectric, the formula can be simplified to:
should be determined by simulating with extracted parasitics from the layout.
eL = (package_length/1000/25.4) * (154 / 174)
where 174 is substituted with a value based on the user’s PCB.
So, if an IXP2800 package length were 18863 µm, eL = 0.657 inches.
L2, L3, L4, and L5 are the actual lengths of the PCB etch in inches.
Loopclock Length=[ Mean(eL1 + L2 + L3) ] + [ Mean( L4 + L5 + eL6) ] + 3.1 in.
Hardware Design Guide

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