EWIXP425BCT Intel, EWIXP425BCT Datasheet - Page 74

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EWIXP425BCT

Manufacturer Part Number
EWIXP425BCT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP425BCT

Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
Table 16.
Note:
7.1.1
Intel
Hardware Design Guidelines
74
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
SDRAM Address/Data/Control Routing Guidelines
Since all designs are unique, consult your SDRAM component vendor for routing and
layout recommendations.
To ensure the signal quality and functionality of the SDRAM bus, it is strongly
recommended that signal integrity simulations must be performed.
PC 133 SDRAM Clock
These are the general clock guidelines:
Figure 29
• Look carefully at signal line lengths and try to match them as closely as possible.
• Pay particular attention to data bus layout.
• Hand-route critical path signals if possible.
• Dedicate power and ground planes with bypass caps placed as close as possible to
• One via for each power and ground pin per device is highly recommended
• 25-mil traces for power and ground pins is highly recommended and should not be
• Clock signals must have 1-4 SDRAM loads with 3.3-pF cap load
• PCB Impedance: 50 Ω ± 10%
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_DQM[3:0]
the SDRAMs.
less than 10 mil
SDM_CAS_N
SDM_RAS_N
SDM_CS_N0
SDM_CS_N1
SDM_WE_N
SDM_CKE
Intel
SIGNAL
®
shows the PC 133 SDRAM clock topology.
IXP42X product line and IXC1100 control plane processors—Critical Routing Topologies
Top
2
1
1
1
1
3
1
.
Trace (Mils)
Widt
10
10
h
5
5
5
5
5
Spacin
10
10
10
10
10
10
10
g
Min
0.2
0.2
0.2
0.2
0.2
A
Max
3.5
3.5
3.5
3.5
3.5
Min
0.2
0.2
0.2
0.2
0.2
Trace Lengths (Inches)
B
Max
1.0
1.0
1.0
1.0
1.0
Document Number: 252817-008US
Min
0.2
C
Max
3.5
December 2007
Min
3.7
D
Max
1.0

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