GWIXP465BAB Intel, GWIXP465BAB Datasheet - Page 141

• Manufacturer Part Number: GWIXP465BAB
• Manufacturer: Intel

Specifications of GWIXP465BAB

• Core Operating Frequency: 266MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

5.6.2.7.2
Figure 33.
Table 66.
Intel
Document Number:
®
IXP45X and Intel
Expansion Bus Asynchronous Operation
Intel Multiplexed Mode
Intel Multiplexed Mode Values (Sheet 1 of 2)
Talepulse
Tale2addrhold
Tdval2valwrt
Twrpulse
Tdholdafterwr
Tale2valcs
NOTES:
1. The EX_ALE signal is extended form T to 4T nnsec based on the programming of the T1 timing parameter.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
7. T is the period of the clock measured in ns.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
9. Timing was designed for a system load between 5pF and 60pF for high drive setting
306261-002
The parameter Tale2addrhold is fixed at T.
strobe (read or write) to an external device.
write) to an external device. Data will be available during this time as well.
data (during a write) will be held.
expansion interface.
synchronous mode.
Symbol
®
EX_WR_N
EX_ADDR
EX_RD_N
EX_CS_N
EX_DATA
EX_DATA
IXP46X Product Line of Network Processors Datasheet
EX_CLK
EX_ALE
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
Valid address hold time after from falling edge of ALE
Write data valid prior to WR_N falling edge
Pulse width of the WR_N
Valid data after the rising edge of WR_N
Valid chip select after the falling edge of ALE
T alepulse T ale2valcs
ALE Extended
Address
2-5 Cycles
Address
Multiplexed Address/Data
T1
T ale2addrhold
Parameter
T dval2valwrt
Valid Address
1-4 Cycles
T2
1-16 Cycles
Output Data
T wrpulse
T rdsetup
T3
Input Data
T dhold2afterwr
1-4 Cycles
T4
Electrical Specifications
T rdhold
Min.
1
1
1
1
1
1
1-16 Cycles
T recov
Max.
T5
16
1
4
4
4
4
Cycles 1,
Cycles 1, 2,
Cycles 3,
Cycles 4,
Cycles 5,
Cycles
Units
A9585-01
May 2005
7
Notes
7
7
7
7
7
141