EWIXP465BAET Intel, EWIXP465BAET Datasheet - Page 31

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EWIXP465BAET

Manufacturer Part Number
EWIXP465BAET
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP465BAET

Core Operating Frequency
667MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EWIXP465BAET
Manufacturer:
ATMEL
Quantity:
1 000
3.1.18
3.1.19
3.1.20
Intel
Document Number:
®
IXP45X and Intel
The SSP operates in master mode (the attached peripheral functions as a slave), and supports serial
bit rates from 7.2 Kbps to 1.8432 Mbps using the on-chip, 3.6864-MHz clock, and bit rates from
65.10 Kbps to 16.67 Mbps using a maximum off-chip, 33.33 MHz clock. Serial data formats may
range from 4 to 16 bits in length. Two on-chip register blocks function as independent FIFOs for
data, one for each direction. The FIFOs are 16 entries deep x 16 bits wide. Each 32-bit word from
the system fills one entry in a FIFO using the lower half 16-bits of a 32-bit word.
I
The I
and slave device residing on the I
for input and output functions and SCL is the clock pin for reference and control of the I
The I
and micro-controllers for system management functions. The serial bus requires a minimum of
hardware for an economical system to relay status and reliability information on the IXP45X/
IXP46X network processors subsystem to an external device.
The I
processors’ APB. Data is transmitted to and received from the I
Control and status information is relayed through a set of memory-mapped registers. Refer to the
I
The I
The I
100 Kbps. Fast mode logic levels, formats, capacitive loading and protocols function the same in
both modes. The I
AES/DES/SHA/MD-5
The IXP45X/IXP46X network processors implement on-chip hardware acceleration for underlying
security and authentication algorithms.
The encryption/decryption algorithms supported are AES, single pass AES-CCM, DES, and triple
DES. These algorithms are commonly found when implementing IPSEC, VPN, WEP, WEP2,
WPA, and WPA2.
The authentication algorithms supported are MD-5, SHA-1, SHA-256, SHA-384, and SHA-512.
Inclusion of SHA-384 and SHA-512 allows 256-bit key authentication to pair up with 256-bit AES
support.
Cryptography Unit
The Cryptography Unit implements three major functions:
2
2
306261-002
C Bus Specification for complete details on I
C Interface
®
Multi-master capabilities
Slave capabilities
Exponentiation Unit (EAU)
Random Number Generator (RNG)
Secure Hash Algorithm (SHA function for the RNG)
2
2
2
2
2
IXP46X Product Line of Network Processors Datasheet
C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a master
C bus allows the IXP45X/IXP46X network processors to interface to other I
C Bus Interface Unit is a peripheral device that resides on the IXP45X/IXP46X network
C supports:
C unit supports both fast-mode operation — at 400 Kbps — and standard mode — at
2
C unit does not support I
2
C bus. The I
2
C 10-bit addressing or CBUS.
2
2
C bus is a two-pin serial bus. SDA is the data pin
C bus operation.
2
C bus via a buffered interface.
Functional Overview
2
C peripherals
2
C bus.
May 2005
31

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