EWIXP465BAET Intel, EWIXP465BAET Datasheet - Page 62

• Manufacturer Part Number: EWIXP465BAET
• Manufacturer: Intel

Specifications of EWIXP465BAET

• Core Operating Frequency: 667MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Package Information
Table 15.
May 2005
62
UTP_IP_CLK /
ETHA_RXCLK
UTP_IP_FCI
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† For information on selecting the desired interface, see the Intel
Name
see
Table 1 on page
UTOPIA Level 2/MII_A/ SMII[4] Interface (Sheet 4 of 9)
Power
Reset
on
Z
Z
14.
†
Reset
VI
VI
Table 10 on page
†
Software
Enables
Normal
Reset
After
Until
VI
VI
46.
Software
Enables
Normal
After
®
VI
VI
IXP45X and Intel
®
IXP45X and Intel
Type
I
I
†
UTOPIA Mode of Operation:
UTOPIA Receive clock input. Also known as UTP_RX_CLK.
This signal is used to synchronize all UTOPIA-received inputs to the rising edge of the
UTP_IP_CLK.
MII Mode of Operation:
Externally supplied receive clock.
This MAC interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Not used.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
UTOPIA Input Data flow control input signal. Also known as RXEMPTY/CLAV.
Used to inform the processor of the ability of each polled PHY to send a complete cell. For cell-
level flow control in an MPHY environment, RxClav is an active high tri-stateable signal from the
MPHY to ATM layer. The UTP_IP_FCI, which is connected to multiple MPHY devices, will see
logic high generated by the PHY, one clock after the given PHY address is asserted, when a full
cell can be received by the PHY. The UTP_IP_FCI will see a logic low generated by the PHY, one
clock cycle after the PHY address is asserted if a full cell cannot be received by the PHY.
In SPHY mode, this signal is used to indicate to the processor that the PHY has an octet or cell
available to be transferred to the processor.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel
being used in a system design, this interface/signal is not required for any connection.
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP46X Product Line of Network Processors Developer’s Manual.
®
Intel
IXP46X Product Line of Network Processors Developer’s Manual) and is not
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002
®