GWIXP425ABBT Intel, GWIXP425ABBT Datasheet - Page 24

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GWIXP425ABBT

Manufacturer Part Number
GWIXP425ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP425ABBT

Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant

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2.1.14
2.1.15
2.2
Intel
Datasheet
24
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale
Intel 0.18-micron production semiconductor process technology. This process
technology enables the Intel XScale
power range, producing industry-leading mW/MIPS performance.
Intel XScale
Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal
timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task
scheduling and prevent software lock-ups. The device has four 32-bit counters:
AHB Queue Manager
The AHB Queue Manager (AQM) provides queue functionality for various internal
blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale
processor. The AHB interface is used for configuration of the AQM and provides access
to queues, queue status and SRAM. Individual queue status for queues 0-31 is
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale
Intel XScale
The Intel XScale technology is compliant with the ARM
architecture (ISA). The Intel XScale
• Seven/eight-stage super-pipeline promotes high-speed, efficient processor
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch
• 32-entry instruction memory-management unit for logical-to-physical address
• 32-entry data-memory management unit for logical-to-physical address
• 32-Kbyte instruction cache can hold entire programs, preventing processor stalls
• 32-Kbyte data cache reduces processor stalls caused by multi-cycle memory
• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing”
• Four-entry fill-and-pend buffers to promote processor efficiency by allowing
• Eight-entry write buffer allows the processor to continue execution while data is
• Watch-Dog Timer
performance
choices
translation, access permissions, I-cache attributes
translation, access permissions, D-cache attributes
caused by multi-cycle memory accesses
accesses
of the D-cache
“hit-under-miss” operation with data caches
written to memory
®
processor features include:
®
Intel
Processor
®
processor (or any other AHB bus master), a Flag Bus interface,
®
IXP42X product line and IXC1100 control plane processors—Datasheet
• Timestamp Timer
®
®
processor, shown in
processor to operate over a wide speed and
*
• Two general-purpose
Version 5TE instruction-set
Figure
timers
Document Number:
6, is designed with
®
252479-007US
processor.
June 2007
®

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