EWIXP425BBT Intel, EWIXP425BBT Datasheet - Page 123

• Manufacturer Part Number: EWIXP425BBT
• Manufacturer: Intel

Specifications of EWIXP425BBT

• Core Operating Frequency: 266MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Intel
Table 66.
5.5.2.9
Figure 43.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
High-Speed, Serial Timing Values
For more information on the HSS Jitter Specifications see the Intel
Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.
JTAG
Boundary-Scan General Timings
Notes:
1.
2.
3.
4.
5.
6.
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
T9
HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the
IXP42X product line and IXC1100 control plane processors. The signals are shown to be synchronous
for illustrative purposes and are not required to be synchronous.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source
as inputs into the IXP42X product line and IXC1100 control plane processors. Always applicable to
HSS_RXDATA.
The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of
the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK
and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X
product line and IXC1100 control plane processors to an external source. Always applicable to
HSS_TXDATA.
The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X
product line and IXC1100 control plane processors. The slowest clock speed that can be accepted or
driven is 512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock
duty cycle accepted will be 50/50 + 20%.
Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor.
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the rising edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the rising edge of clock
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the falling edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the falling edge of clock
Rising edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Falling edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after rising edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after falling edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
HSS_TXCLK period and HSS_RXCLK period
JTG_TMS, JTG_TDI
Intel
JTG_TDO
JTG_TCK
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Parameter
T
bsoh
T
T
bsod
bsel
T
bsis
T
bsih
T
bsch
1/8.192 MHz 1/512 KHz
Min.
5
0
5
0
0
0
®
Max.
15
15
IXP42X Product
Units
B0416-01
ns
ns
ns
ns
ns
ns
ns
ns
ns
Datasheet
Notes
1, 2,
1, 2,
1, 2,
1, 2,
1, 3,
1, 3,
1, 3,
1,
5
123
4
3
3
3
3
4
4
4