EWIXP425BBT Intel, EWIXP425BBT Datasheet - Page 39

• Manufacturer Part Number: EWIXP425BBT
• Manufacturer: Intel

Specifications of EWIXP425BBT

• Core Operating Frequency: 266MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Intel
Table 10.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
High-Speed, Serial Interface 1
HSS_TXFRAME1
HSS_TXDATA1
HSS_TXCLK1
HSS_RXFRAME1
HSS_RXDATA1
HSS_RXCLK1
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Reset
Reset
Intel
Z
Z
Z
Z
Z
Z
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Reset
Post
VI
Z
Z
Z
Z
Z
Type
O/D
I/O
I/O
I/O
I/O
I
Table 5 on page
†
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high
being utilized in the system.
Transmit data out. Open Drain output.
Must be pulled high with a 10-KΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to
clock out the transmitted data. Configured as an input upon
reset. Frame sync and Data can be selected to be generated
on the rising or falling edge of the transmit clock.
Should be pulled high
being utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high
being utilized in the system.
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
Should be pulled high
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
Should be pulled high
being utilized in the system.
33.
††
††
††
††
††
Description
with a 10-KΩ resistor when not
with a 10-KΩ resistor when not
with a 10-KΩ resistor when not
through a 10-KΩ resistor when not
with a 10-KΩ resistor when not
CCP
.
Datasheet
39