CY7C53120L8-44AXI Cypress Semiconductor Corp, CY7C53120L8-44AXI Datasheet - Page 4

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CY7C53120L8-44AXI

Manufacturer Part Number
CY7C53120L8-44AXI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C53120L8-44AXI

Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Manufacturer
Quantity
Price
Part Number:
CY7C53120L8-44AXI
Quantity:
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Document #: 38-10002 Rev. *E
Pin Definitions
Memory Usage
All Neuron chips require system firmware to be present when
they are powered up. In the case of the CY7C53120L8, this
firmware is preprogrammed in the factory in an on-chip ROM.
In the case of the CY7C53150L, the system firmware must be
present in the first 16KBytes of an off-chip nonvolatile memory
such as Flash, EPROM, EEPROM, or NVRAM. Because the
system firmware implements the network protocol, it cannot
itself be downloaded over the network.
For the CY7C53120L8, the user application program is stored
in on-chip Flash memory. It may be programmed using a
device programmer before board assembly, or may be
programmed in-circuit after board assembly through a propri-
etary 11-pin programming interface or over the LonTalk
network from an external network management tool.
For the CY7C53150L, the user application program is stored
in on-chip Flash Memory and also in off-chip memory. The
Notes:
SCLK/RXD I/O
MISO
MOSI/TXD I/O
D0–D7
R/W
E
A0–A15
V
V
CV
V
CP0–CP4
NC
4. Power supply sequencing is required. Power must be applied such that, V
5. For detailed information about data retention after 100K cycles, please see Cypress qualification report.
Pin Name
DD
SS
PP
until V
DD
[4]
DD
reaches its normal operating voltage. Ramps can be simultaneous as long as the above condition is maintained.
I/O
Output
I/O
Output
Output
Input
Input
Input
Input
Communication
Network Interface
(continued)
I/O
SPI Clock or UART RXD. Muxed with IO8. Can
be configured as Open Drain Output.
SPI Master In/Slave Out (MISO) Muxed with
IO9. Can be configured as Open Drain Output.
SPI Master out/Slave In (MOSI) or UART
TXD. Muxed with IO10. Can be configured as
Open Drain Output.
Bidirectional memory data bus.
Read/write control output for external
memory.
Enable clock control output for external
memory.
Memory address output port.
Power input (3.3V nom.). All V
connected together externally.
Power input (0V, GND). All V
connected together externally.
Power input, 5V or 3.3V depending on
Communications Port Voltage.
In-circuit test mode control. If V
when RESET is asserted, the I/O, address and
data buses become Hi-Z.
Bidirectional port supporting communica-
tions in three modes.
No connect. Must not be connected on the
user’s PC board, since they may be connected
internal to the chip.
Pin Function
DD
SS
(3.3V) supply must not trail CV
DD
user program may initially be programmed into the off-chip
memory device using a device programmer.
Flash Memory Retention and Endurance
Data and code stored in Flash Memory is guaranteed to be
retained for at least ten years for programming temperature
range of –40°C to 85°C.
The Flash memory can typically be written 100,000 times
without any data loss
system firmware extends the effective endurance of the Flash
memory in two ways. If the data being written to a byte of Flash
memory is the same as the data already present in that byte, the
firmware does not perform the physical write. So for example,
an application that sets its own address in Flash memory after
every reset will not use up any write cycles if the address has
not changed. In addition, system firmware version 15 or higher is
pins must be
pins must be
PP
is high
CY7C53150L
43, 42, 38, 37,
36, 35, 34, 33
64, 63, 62, 61,
60, 59, 58, 57,
56, 55, 54, 53,
52, 51, 50, 47
28, 29, 30, 31,
1, 18, 27, 48,
8,19, 21, 25,
40, 41, 44
TQFP-64
7, 20, 22,
Pin No.
14
15
16
45
46
39
26
32
49
[5]
DD
9
. An erase/write cycle takes 20 ms. The
(3.3V/5V) supply on power-up by more than 1V
CY7C53120L8
19, 20, 17, 21,
9, 13, 16, 23,
2, 11, 12,
SOIC-32
Pin No.
25, 32
N/A
N/A
N/A
N/A
27
26
24
31
18
10
22
CY7C53120L8
CY7C53150L
1, 6, 11, 12, 17,
20, 21, 18, 24,
22, 23, 28, 33,
CY7C53120L
7,13, 16, 26,
Page 4 of 14
8 TQFP-44
29, 38, 41
34, 39, 44
Pin No.
9, 10,
N/A
N/A
N/A
N/A
31
30
27
37
19
25
8

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