CY7C53120L8-44AXI Cypress Semiconductor Corp, CY7C53120L8-44AXI Datasheet - Page 8

• Manufacturer Part Number: CY7C53120L8-44AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C53120L8-44AXI

• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Document #: 38-10002 Rev. *E
External Memory Interface Timing — CY7C53150L, V
Differential Transceiver Electrical Characteristics
t
PW
PW
t
t
t
t
t
t
t
t
t
t
t
t
t
Receiver Common Mode Voltage Range to maintain hysteresis
Receiver Common Mode Range to operate with unspecified hysteresis
Input Offset Voltage
Propagation Delay (F = 0, V
Input Resistance
Wake-up Time
Differential Output Impedance for CP2 and CP3
Receiver Common Mode Voltage Range to maintain hysteresis
Receiver Common Mode Range to operate with unspecified hysteresis
Input Offset Voltage
Propagation Delay (F = 0, V
Input Resistance
Wake-up Time
Differential Output Impedance for CP2 and CP3
Notes:
16. t
17. Refer to Figure 3 for detailed measurement information.
18. The data hold parameter, t
19. Refer to Figure 5 and Figure 4 for detailed measurement information.
20. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information.
21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs.
22. Z
cyc
AD
AH
RD
RH
WR
WH
DSR
DHR
DHW
DDW
DHZ
DDZ
acc
Parameter
cyc
EH
EL
0
= {Sum of DC drop across CP2 and CP3 pads @40mA current} / 40mA for CVdd +/-5%.
= 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz).
Memory Cycle Time (System Clock Period)
Pulse Width, E High
Pulse Width, E Low
Delay, E High to Address Valid
Address Hold Time After E High
Delay, E High to R/W Valid Read
R/W Hold Time Read After E High
Delay, E High to R/W Valid Write
R/W Hold Time Write After E High
Read Data Setup Time to E High
Data Hold Time Read After E High
Data Hold Time Write After E High
Delay, E Low to Data Valid
Data Three State Hold Time After E Low
Delay, E High to Data Three-State
External Memory Access Time (t
20-MHz input clock
DHW
Characteristic at 3.3V
Characteristic at 5V
, is measured to the disable levels shown in Figure 4, rather than to the traditional data invalid levels.
ID
ID
= V
= V
hys
hys
[17]
[17]
/2 + 200 mV)
/2 + 200 mV)
Description
acc
[22]
[22]
[19]
[18, 19]
= t
cyc
[20]
– t
[16]
AD
– t
[21]
[21]
DSR
DD
) at
± 10%
–0.05V
–0.05V
(V
Min.
Min.
DD
t
t
0.6
0.4
1.2
0.9
—
—
—
—
cyc
cyc
5
5
hys
hys
Min.
100
= 3.0V to 3.6 V, T
/2 – 5
/2 – 5
—
10
—
—
15
10
—
—
50
5
5
0
0
– 35
– 35
0.05V
0.05V
CY7C53120L8
V
V
V
V
t
t
DD
CY7C53150L
230 ns
230 ns
cyc
cyc
DD
DD
DD
A
Max.
Max.
Max.
3200
= –40°C to+ 85°C
10
35
10
35
—
—
hys
hys
– 1.75
/2 + 5
/2 + 5
35
—
25
—
25
—
—
—
—
12
—
42
—
– 1.5
– 1.3
– 2.2
+ 35
+ 35
Page 8 of 14
Unit
Unit
Unit
MΩ
MΩ
mV
mV
ns
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ω
Ω
V
V
V
V
[1]
)