GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 70

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Package Information
Table 16.
May 2005
70
ETHB_RXDATA[3:0] /
SMII_RXDATA[0] /
SMII_RXDATA[1] /
SMII_RXDATA[2] /
SMII_RXDATA[3]
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† Please refer to Intel
Name
see
Table 1 on page
MII/SMII Interfaces (Sheet 3 of 8)
®
IXP45X and Intel
Power
Reset
on
Z
14.
Reset
VI
Table 10 on page
®
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
Software
Enables
Normal
Reset
After
Until
VI
46.
Software
Enables
Normal
After
®
VI
IXP45X and Intel
Type
I
MII Mode of Operation:
Receive data bus from PHY, data sampled synchronously with respect to ETHB_RXCLK. This
MAC interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Each SMII_RXDATA line is a separate physical port
ETHB_RXDATA[3] is multiplexed with SMII_RXDATA[3],
ETHB_RXDATA[2] is multiplexed with SMII_RXDATA[2],
ETHB_RXDATA[1] is multiplexed with SMII_RXDATA[1],
ETHB_RXDATA[0] is multiplexed with SMII_RXDATA[0]
The data on these signal are received synchronously with respect to the rising edge of SMII_CLK
when operating as an SMII interface and synchronously with respect to the rising edge of
SMII_RXCLK when operating as a Source Synchronous SMII interface
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B
Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of
the Intel
and is not being used in a system design, this interface/signal is not required for any connection.
One special configuration exists for the board designer. When NPE B is configured in SMII mode
of operation and a subset of the four SMII ports are utilized (i.e. All four are enabled but only two
are being connected). The unused inputs must be tied high with a 10-KΩ resistor.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP45X and Intel
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Developer’s Manual)
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002

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