PRIXP425ABC 885156 Intel, PRIXP425ABC 885156 Datasheet - Page 20

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PRIXP425ABC 885156

Manufacturer Part Number
PRIXP425ABC 885156
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425ABC 885156

Lead Free Status / Rohs Status
Supplier Unconfirmed
3.1.1
Table 2.
3.1.2
Table 3.
Intel
Hardware Design Guidelines
20
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
SDRAM Interface Signals
SDRAM Interface Signals
SDRAM Block Diagrams
The IXP42X product line and IXC1100 control plane processors support the PC133-
compatible SDRAM 16 and 32-bit wide devices. The banks are accessed 32 bits at a
time. The maximum configuration is two physical banks of SDRAM devices (each bank
consists of two SDRAM 16-bit devices or single SDRAM 32-bit device), using two
independent chip-selects.
The supported memory types are listed in
support a maximum of 256 Mbytes of SDRAM and a minimum of 8 Mbytes, using two
SDRAM devices. The PC133 SDRAM memory bus I/O buffers are designed to support up
to four loads total for two banks of PC133 of SDRAM memory.
SDRAM Memory Types
Note:
Note:
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CS_N[1:0]
SDM_DQM[3:0]
Technology
SDM_CLKOUT
SDM_BA[1:0]
SDM_RAS_N
SDM_CAS_N
SDM_WE_N
SDRAM
64 Mbit
SDM_CKE
Intel
Name
For explanations of the
The 4 M x 32, * 8 M x 32 and * 16 M x 32 devices have not been fully validated by Intel.
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Arrangement
Type*
I/O
SDRAM
2M x 32
2M x 32
4M x 16
4M x 16
O
O
O
O
O
O
O
O
O
Type
SDRAM Address: A0-A12 are output during the READ/WRITE command
and ACTIVE command to select a location in memory.
SDRAM Data: bidirectional data bus used to transfer data to and from the
SDRAM.
SDRAM Clock: All SDRAM input signals are sampled on the rising edge of
SDM_CLKOUT. All output signals are driven with respect to the rising edge
of the Clock.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the
current command is accessing.
SDRAM Row Address strobe/select (active low): Along with SDM_CAS_N,
SDM_WE_N, and SDM_CS_N signals determines the current command to
be executed.
SDRAM Column Address strobe/select (active low): Along with
SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals determines the current
command to be executed.
SDRAM Chip select (active low): CS# enables the command decoder in the
external SDRAM when logic low and disables the command decoder in the
external SDRAM when logic high.
SDRAM Write enable (active low): Along with SDM_CAS_N, SDM_RAS_N,
and SDM_CS_N signals determines the current command to be executed.
SDRAM Clock Enable: CKE is driving high to activate the clock to an
external SDRAM and driver low to de-activate the CLK to an external
SDRAM.
SDRAM Data bus mask: DQM is used to bytes select data during read/write
access to an external SDRAM.
column abbreviations, see
Number of Chips
1
2
2
4
Table
3. The processors’ SDRAM interfaces
Number of Banks
Description
Table 21 on page
(Systems)
1
2
1
2
Document Number: 252817-008US
81.
Total Memory Size
16 Mbytes
16 Mbytes
32 Mbytes
8 Mbytes
Considerations
December 2007

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