PRIXP425ABC 885156 Intel, PRIXP425ABC 885156 Datasheet - Page 69

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PRIXP425ABC 885156

Manufacturer Part Number
PRIXP425ABC 885156
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425ABC 885156

Lead Free Status / Rohs Status
Supplier Unconfirmed
General Layout and Routing Guide—Intel
processors
6.3.6
6.3.7
December 2007
Document Number: 252817-008US
Trace Impedance
All signal layers require controlled impedance of 50 Ω ±10 % microstrip or stripline
where appropriate unless otherwise specified. Selecting the appropriate board stack-up
to minimize impedance variations is very important. When calculating flight times, it is
important to consider the minimum and maximum trace impedance based on the
switching neighboring traces. Wider spaces between traces may be used since this can
minimize trace-to-trace coupling, and reduce cross talk.
All recommendations, described in this document assume a 5-mil 50 Ω ± 10% signal
trace unless otherwise specified. When a different stack up is used the trace widths
must be adjusted appropriately. When wider traces are used, the trace spacing must be
adjusted accordingly (linearly). It is highly recommended that a 2D Field Solver be
used to design the high-speed traces.
Power and Decoupling
The power planes should have ample decoupling to ground to minimize the effects of
the switching currents. The decoupling should consist of three types: the bulk, the
high-frequency ceramic, and the inter-plane capacitors.
• Carefully match the type and value of capacitor to the range of frequencies it must
• Place all components associated with one clock trace closely together. This reduces
• Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors
• For fast switching currents, high-frequency low-inductance capacitors are most
• Use an inter-plane capacitor between power and ground planes to reduce the
• Uniformly distributed and connected across the power planes on the PCB.
• Provide Power (Vcc) Island and Vss, and Vccp and Vss on the package and PCB.
• Insert additional pairs of Vccp, Vssp for longer (corner) traces in the package.
• Place Vccp/Vss pins and I/Os on the outer rows of the package to avoid crossing
• Place Vcc/Vss pads in pairs and place processor Vcc/Vss near the center of the
• Separately route Vcc internal to package and on the die and use symmetry for
• It is recommended that with the requirements for 1.3 V and 3.3 V supplies for the
bypass (i.e., tantalum capacitors are more effective at higher frequencies than
aluminum electrolytic capacitors, and capacitors of different values are effective at
different frequencies).
the trace length and reduces radiation.
supply large reservoirs of charge, but are only useful at lower frequencies due to
lead inductance effects. The bulk capacitors can be located anywhere on the board.
effective. These capacitors should be placed as close to the device being decoupled
as possible. This minimizes the parasitic resistance and inductance associated with
board traces and vias.
effective plane impedance at high frequencies. The general guideline for placing
capacitors is to place high-frequency ceramic capacitors as close as possible to the
module.
Use symmetry for I/O pads and Vccp/Vss return.
the split in Vcc planes.
package.
processor Vcc/Vss pads and pins.
IXP42X product line and IXC1100 control plane processors, it is not necessary to
add completely new power supply layers to the circuit board to facilitate this. It is
possible to create supply ‘islands’ underneath the processor in the existing power
supply plane.
Intel
®
®
IXP42X product line and IXC1100 control plane
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Hardware Design Guidelines
69

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