CY7C53120L8-44AI Cypress Semiconductor Corp, CY7C53120L8-44AI Datasheet
CY7C53120L8-44AI
Specifications of CY7C53120L8-44AI
Available stocks
Related parts for CY7C53120L8-44AI
CY7C53120L8-44AI Summary of contents
Page 1
... Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware-based protocol stored in 16KBytes ROM (CY7C53120L8), or off-chip memory (CY7C53150L). The firmware also contains 38 prepro- grammed I/O drivers, simplifying application programming. The application program is stored in the Flash memory (CY7C53120L8) and/or off-chip memory (CY7C53150L), and may be updated by downloading over the network ...
Page 2
... No Connect (NC) — should not be used. (These pins may be used for internal testing.) 3. The smaller dimple at the bottom left of the marking indicates pin 1. Document #: 38-10002 Rev. *E CY7C53150L 64-lead Thin Quad Flat Pack CY7C53150L-64AI CY7C53120L8 CY7C53150L 32 CP4 CP3 31 30 CP2 29 CP1 28 CP0 [ CLK1 24 23 CLK2 ...
Page 3
... SS IO9/MISO [ IO10/MOSI/TXD RESET CP4 DD CP3 42 IO4 CP1 IO3 43 CP0 [ CP2 1 PIN 1 INDICATOR Pin Function CY7C53120L8 CY7C53150L 44-lead TQFP CY7C53120L8-44AI CY7C53150L CY7C53120L8 TQFP-64 SOIC-32 Pin No. Pin No 10, 11, 12 30, 29, 28 14, 15, 16 27, 26 [2] NC CP1 CP0 CV DD CP2 [ CLK1 CLK2 V SS [2] NC ...
Page 4
... Memory Usage All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120L8, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150L, the system firmware must be present in the first 16KBytes of an off-chip nonvolatile memory such as Flash, EPROM, EEPROM, or NVRAM ...
Page 5
... RESET is an Input/Output pin 5V-tolerant input pin. It can provide 5V-compatible levels when output if an external resistor is connected between pin and 5V supply. Note: 6. Please see document Errata for CY7C53150L and CY7C53120L8 - 3.3V Neuron Chip (38-17019) for details. Document #: 38-10002 Rev. *E CY7C53120L8 Hardware Serial Communication Engine The CY7C53120L8/3150L features a hardware Serial Communication Engine ...
Page 6
... Filter ( Receiver across hysteresis) Filter ( 5V, there will be a ≥ Differential Receiver (End-to-End) Absolute Symmetry Filter (F) Hysteresis ( Time from input switching states from high to low to output switching states. PHL CY7C53120L8 CY7C53150L [7] V Min. V Typ. hys hys 0.019 V 0.027 0.038 V 0.054 ...
Page 7
... LVI Trip Point ( Part Number CY7C53120L8, and CY7C53150L Notes: 12. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150L, standard outputs also include A0–A15, D0–D7, E, and R/W. 13. IO4–IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up. ...
Page 8
... DC drop across CP2 and CP3 pads @40mA current} / 40mA for CVdd +/-5%. 0 Document #: 38-10002 Rev. *E ± 10% DD Description [16] [18, 19] [20] [19 – t – acc cyc AD DSR [21 200 mV) [22] [21 200 mV) [22] CY7C53120L8 CY7C53150L (V = 3. –40°C to+ 85° Min. Max. 100 3200 t /2 – cyc cyc t /2 – cyc cyc — ...
Page 9
... Document #: 38-10002 Rev for for A0–A15, D0–D7, and R for all other signals 2.0V 0.8V 2.0V 0. 2.0V 0.8V V – – Measured high output drive level OH V – Measured low output drive level OL V TEST SIGNAL 1.4mA L LOAD CY7C53120L8 CY7C53150L PW EL 2.0V /2 Page ...
Page 10
... Figure 7. External Memory Interface Timing Diagram Document #: 38-10002 Rev Address DSR Data In t DHR t t DDW DHR t DHZ Memory READ Memory WRITE CY7C53120L8 CY7C53150L t AD Address Address DDW t t DDZ DDZ t DHZ t DHW t DHW Data Out Data Out Memory WRITE Page ...
Page 11
... Common-Mode voltage: Vcm = ( V(CP0) + V(CP1 Hysteresis Voltage [Vtrip+] - [Vtrip-] Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 3.3V Operation Document #: 38-10002 Rev V(CP0 V(CP1) V(CP0)-V(CP1) 1 Vtrip+ Vtrip V(CP0 V(CP1) V(CP0)-V(CP1) Vtrip+ Vtrip- CY7C53120L8 CY7C53150L Time Time 5V 0V Time Time 3.3V 0V Page ...
Page 12
... Ordering Information Flash Part Number (KBytes) CY7C53150L-64AI 2.75 CY7C53120L8-32SI 8 CY7C53120L8-44AI 8 Package Diagrams 64-lead Thin Plastic Quad Flat Pack (14 × 14 × 1.4 mm) A65 Document #: 38-10002 Rev. *E Max. Input ROM SRAM Clock (KBytes) (KBytes) (MHz CY7C53120L8 CY7C53150L Package Name Package Type A65 64-lead Thin Plastic Quad Flat Pack ...
Page 13
... Cypress against all charges. 44-lead Thin Plastic Quad Flat Pack A44 32-Lead (450 MIL) Molded SOIC S34 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.004[0.102] MIN. SEATING PLANE CY7C53120L8 CY7C53150L 51-85064-*B 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*B Page ...
Page 14
... Clarified Reset Stretch times Corrected pin definitions (pins 10 to 14) on 100pin TQFP diagram Added Theta-JA value for the 100-pin TQFP package Changed part numbers to CY7C53120L8 / CY7C53150L Added ordering information table TGE Add footnote #4 on Power supply considerations Corrected Theta-JA values for all packages ...