EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 24

• Manufacturer Part Number: EWIXP420ABBT
• Manufacturer: Intel

Specifications of EWIXP420ABBT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 5.
3.1.3
Intel
Hardware Design Guidelines
24
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 5
interfaces to two banks (4 Chips) of the PC133 SDRAM using the 8 M x 16 (128-Mbit),
16 M x 16 (256-Mbit), or 32 M x 16 (512-Mbit).
Dual Bank SDRAM System Block Diagram (x16 Devices)
SDRAM Initialization
Initialization of the SDRAM devices is performed by the operating system. The following
sequence must be followed:
• The memory controller applies the clock enable pin (SDM_CKE) during power up
• The memory controller holds all the control pins to the memory inactive
• SDM_CKE is driven to VCC all the time. The IXP42X product line and IXC1100
• Software disables the refresh counter by setting the SDRAM Refresh
• Software issues one NOP cycle after the 1ms SDRAM device deselect. A NOP is
• Software pauses 200 µs after the NOP.
Plane Processors
IXP42X Product
and must stabilize the clock signal within 100 µs after power stabilizes.
(SDM_RAS_N, SDM_CAS_N, SDM_WE_N, SDM_CS_N[1:0]=1) for a minimum of
1 ms after supply voltage reaches the desired level.
control plane processors never de-assert SDM_CKE
(SDR_REFRESH) Register to zero.
accomplished by setting the SDRAM Instruction (SDR_IR) Register to 011. The
memory controller asserts SDM_CKE with the NOP.
SDM_ADDR[12: 0]
and IXC 1100
SDM_DATA[31: 0]
SDM__DQM[3:0]
SDM_CS_N[1:0]
Intel
SDM_CLKOUT
Control
Intel
SDM_RAS_N
SDM_CAS_N
Line
SDM_BA[1:0]
SDM_WE_N
illustrates how the IXP42X product line and IXC1100 control plane processors’
SDM_CKE
®
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
SDM_CS_N0
SDM_DQM[3:2]
SDM_DQM[1:0]
SMD_DATA[15:0]
CS#
A[12:0]
CS#
DQM[1:0]
DQ[15:0]
A[12:0]
RAS#
CAS#
BA[1:0]
DQ[15:0]
RAS#
CAS#
BA[1:0]
CKE
WE#
WE#
CLK
DQM[1:0]
CKE
CLK
SDRAM #1
SDRAM #2
BANK 0
SDM_DATA[15:0]
SDM_DQM[3:2]
SDM_CS_N1
SDM_DATA[16:31]
SDM_DQM[1:0]
SDM_CS_N1
Document Number: 252817-008US
DQ[15:0]
A[12:0]
CS#
RAS#
CAS#
CS#
BA[1:0]
WE#
DQM[1:0]
BA[1:0]
CKE
CLK
DQ[15: 0]
A[12:0]
RAS#
CAS#
DQM[ 1:0]
CKE
CLK
SDRAM #1
WE#
SDRAM #2
BANK 1
Considerations
December 2007
B2249 -02