EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 48

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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12
3.11
3.11.1
Table 12.
3.11.2
3.12
Intel
Hardware Design Guidelines
48
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
JTAG Interface
JTAG is the IEEE Standards 1149.1-1990 and 1149.1a-1993, IEEE Standard Test
Access Port and Boundary-Scan Architecture, with support for:
Refer to the IEEE 1149.1 standard for an explanation of the terms used in this section
and a complete description of the TAP-controller states. The interface is controlled
through five dedicated test access port (TAP) pins: TDI, TMS, TCK, nTRST, and TDO, as
described in
controller, instruction register, boundary-scan register, bypass register, device
identification register, and data-specific registers. These are described in the Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
The IXP42X product line and IXC1100 control plane processors may be controlled
during debug through a JTAG interface to the processor, the debug tools such as the
Macraigor* Raven*, EPI* Majic*, Wind River Systems* visionPROBE* / visionICE* or
various other JTAG tools plug into the JTAG interface through a connector.
Interface Signals
JTAG Interface Signals
Pull-Up/Down Resistors
The IEEE 1149.1 standard effectively requires that JTG_TDI, JTG_TMS, and
JTG_TRST_N have internal pull-up resistors. It is recommended that the JTG_TDI and
JTG_TMS pins be left unconnected when not in use. To initialize JTAG, JTG_TRST_N
must be asserted at power-on. JTG_TRST_N must be tied low in cases where JTAG is
not used.
Clock
The IXP42X product line and IXC1100 control plane processors require a 33.33-MHz
reference clock that generates all processor and most internal peripheral clocks. The
33.33-MHz reference clock may be generated using onboard oscillator or PLL chip. This
clock is multiplied internally by the processors to 133 MHz and driven to the PC133
SDRAM interface.
Note:
• Board-level boundary-scan connectivity testing
• Connection to software debugging tools through the JTAG interface
• In-system programming of programmable memory and logic devices on the PCB
JTG_TRST_N
JTG_TMS
JTG_TDO
JTG_TCK
JTG_TDI
Name
Intel
For explanations of the
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Table
12. The boundary-scan test-logic elements include the TAP pins, TAP
Type*
O
I
I
I
I
Type
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
The JTG_TRST_N signal must be asserted (driven low) during power-up,
otherwise the TAP controller may not be initialized properly, and the
processor may be locked.
When the JTAG interface is not being used, the signal must be pulled low
using a 10-kΩ resistor.
Used as the clock for the IEEE 1149.1 JTAG interface.
column abbreviations, see
Description
Table 21 on page
Document Number: 252817-008US
81.
Considerations
December 2007
®

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