PRIXP420ABD 885159 Intel, PRIXP420ABD 885159 Datasheet - Page 34

• Manufacturer Part Number: PRIXP420ABD 885159
• Manufacturer: Intel

Specifications of PRIXP420ABD 885159

• Lead Free Status / Rohs Status: Compliant

Table 7.
Intel
Hardware Design Guidelines
34
Note:
ETH_RXDATA1[3:0]
®
ETH_RXCLK1
ETH_RXDV1
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
ETH_COL1
ETH_CRS1
Name
For explanations of the
Ethernet Interface Signals (Sheet 2 of 2)
Intel
Type*
I
I
I
I
I
®
Type
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Externally supplied receive clock.
This MAC contains hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Receive data bus from PHY, data sample synchronously with respect to ETH_RXCLK1. This
MAC contains hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data.
This MAC contains hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Asserted by the PHY when a collision is detected by the PHY. This MAC contains hardware
hashing capabilities.
Should be pulled low through a 10-kΩ resistor when not being used in the system.
Asserted by the PHY when the transmit medium or receive medium are active. De-asserted
when both the transmit medium and receive medium are idle. Remains asserted
throughout the duration of collision condition. PHY asserts CRS asynchronously and de-
asserts synchronously with respect to ETH_RXCLK1. This MAC interface contains hardware
hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps
column abbreviations, see
Table 21 on page
Description
81.
Document Number: 252817-008US
Considerations
December 2007