EWIXP460BAD Intel, EWIXP460BAD Datasheet - Page 152

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EWIXP460BAD

Manufacturer Part Number
EWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Electrical Specifications
Table 75.
Figure 40.
May 2005
152
HPI-16 Non-Multiplexed Read Accesses Values
HPI*-16 Non-Multiplexed Read Mode
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
6. One cycle is the period of the Expansion Bus clock.
7. Timing was designed for a system load between 5pF and 60pF for high drive setting
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
T
for the address phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/IXP46X
network processors have had sufficient time to recognize the HRDY and hold the address phase for at
least one clock pulse after the HRDY is de-active.
clocks for setup phase.
for the data phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/IXP46X
network processors have had sufficient time to recognize the HRDY and hold the data setup phase for at
least one clock pulse after the HRDY is de-active
Expansion Bus interface.
until HRDY is de-active
recov
EX_ADDR[23:0]
EX_RDY_N
EX_WR_N
EX_CS_N
EX_RD_N
EX_DATA
(hr_w_n)
(hds1_n)
EX_CLK
(hcs_n)
(hdout)
(hrdy)
Valid time that address is asserted on the line. The address is
asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data strobe
being active.
Pulse width of the HDS1 data strobe
Data is valid from the time from of the falling edge of HDS1_N
to when the data is read.
Time required between successive accesses on the
expansion interface.
Tcs2hds1val
(ha)
T1
Intel
®
IXP45X and Intel
T2
Parameter
Thds1_pulse
Tdata_setup
Valid
Tadd_setup
T3
®
Valid Data
IXP46X Product Line of Network Processors Datasheet
T4
Trecov
T5
T1
Min.
Document Number:
11
3
4
4
2
Max.
45
17
4
5
5
T2
Valid
Cycles
Cycles
Cycles
Cycles
Cycles
Units
Valid Data
306261-002
T3
1, 5, 6
5, 6
2, 4, 5
3, 5, 6
4, 6
Notes
B-01

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