EWIXP460BAD Intel, EWIXP460BAD Datasheet - Page 33

• Manufacturer Part Number: EWIXP460BAD
• Manufacturer: Intel

Specifications of EWIXP460BAD

• Core Operating Frequency: 533MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

3.2
Intel
Document Number:
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IXP45X and Intel
Intel XScale
The Intel XScale technology is compliant with the Intel
architecture (ISA). The Intel XScale core, shown in
production semiconductor process technology. This process technology — with the compactness of
the Intel
and power range, producing industry-leading mW/MIPS performance.
Intel XScale core features include:
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306261-002
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Seven/eight-stage super-pipeline promotes high-speed, efficient core performance
128-entry branch target buffer keeps pipeline filled with statistically correct branch choices
32-entry instruction memory-management unit for logical-to-physical address translation,
access permissions, and Instruction-Cache (I-cache) attributes
32-entry data-memory management unit for logical-to-physical address translation, access
permissions, Data-Cache (D-Cache) attributes
32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by multi-
cycle memory accesses
32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses
2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing” of the D-
cache
Four-entry, fill-and-pend buffers to promote core efficiency by allowing “hit-under-miss”
operation with data caches
Eight-entry write buffer allows the core to continue execution while data is written to memory
Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with
40-bit accumulation for efficient, high-quality media and signal processing
Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle
counter for analysis of hit rates, etc.
This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of
internal bus performance.
JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-
change messages) to debug programs
IXP46X Product Line of Network Processors Datasheet
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StrongARM
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Core
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RISC ISA — enables the Intel XScale core to operate over a wide speed
Figure
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StrongARM
4, is designed with Intel, 0.18-micron
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Version 5TE instruction-set
Functional Overview
May 2005
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