EWIXP460BAD Intel, EWIXP460BAD Datasheet - Page 72

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EWIXP460BAD

Manufacturer Part Number
EWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Package Information
Table 16.
May 2005
72
ETHB_CRS/
SMII_SYNC/
SMII_TXSYNC
ETH_MDIO
ETH_MDC
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† Please refer to Intel
Name
see
Table 1 on page
MII/SMII Interfaces (Sheet 5 of 8)
®
IXP45X and Intel
Power
Reset
on
Z
Z
Z
14.
Reset
Z
Z
Z
Table 10 on page
®
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
Software
Enables
Normal
Reset
After
Until
VI
Z
Z
46.
Software
Enables
Normal
VI / VO
VI / VO
After
®
VB
IXP45X and Intel
Type
I/O
I/O
I/O
MII Mode of Operation:
Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when
both the transmit and receive medium are idle. Remains asserted throughout the duration of a
collision condition. PHY asserts CRS asynchronously and de-asserts synchronously, with
respect to ETHB_RXCLK. This MAC interface does not contain hardware hashing capabilities
local to the interface.
SMII Mode of Operation:
In SMII Mode of Operation, this signal is an output that creates a synchronous pulse once every
10 SMII_CLK reference clocks to signal the start of the next 10 bits of data to be transmitted/
received. SMII_CLK Reference clock operates at 125MHz.
In Source Synchronous mode of operation, a synchronous pulse output created once every 10
SMII_TXCLK clocks to signal the start of the next 10 bits of data to be transmitted. SMII_TXCLK
operates at 125MHz.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B
Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of
the Intel
and is not being used in a system design, this interface/signal is not required for any connection.
In MII mode of operation, this signal is a valid input. In SMII mode of operation this signal is a
valid output.
Management data output. Provides the write data to both PHY devices connected to each MII
interface. An external pull-up resistor of 1.5K ohm is required on ETH_MDIO to properly quantify
the external PHYs used in the system. For specific implementation, see the IEEE 802.3
specification.
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
Management data clock. Management data interface clock is used to clock the MDIO signal as
an output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be
configured to be an output through an Intel API as documented in the Intel
Programmer’s Guide.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP45X and Intel
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Developer’s Manual)
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
®
IXP400 Software
306261-002

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