GWIXP455BAC Intel, GWIXP455BAC Datasheet - Page 24

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GWIXP455BAC

Manufacturer Part Number
GWIXP455BAC
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP455BAC

Core Operating Frequency
400MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Functional Overview
3.1.7
3.1.8
May 2005
24
Note: The IXP455 network processor does not support ECC functionality.
The following is a partial list of features not supported:
PCI Controller
The IXP45X/IXP46X network processors’ PCI controller is compatible with the PCI Local Bus
Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as
either a host or an option (i.e. not the Host). This PCI implementation supports 3.3 V I/O only.
DDRI SDRAM Controller
The IXP45X/IXP46X network processors integrate a high-performance, multi-ported Memory
Controller Unit (MCU) to provide a direct interface between the IXP45X/IXP46X network
processors and their local memory subsystem. The MCU supports:
The DDRI SDRAM interface provides a direct connection to a high-bandwidth and reliable
memory subsystem. The DDRI SDRAM interface is a 32-bit-wide data path.
An 8-bit Error Correction Code (ECC) across each 32-bit word improves system reliability. It is
important to note that ECC is also referred to as CB in many DIMM specifications. The pins on
IXP45X/IXP46X network processors are called DDRI_CB[7:0]. The controller supports the 8 bits
due to the fact that internally it is a 32- or 64-bit controller. However, this implementation of the
controller only supports 32 bits.
The ECC circuitry was designed to operate always on a 64-bit word and when operating in 32-bit
mode, the upper 32 bits are driven to zeros internally. To summarize the impact to the customer, the
full 8 bits of ECC must be stored and read from a memory array in order for the ECC logic to work.
An 8-bit-wide memory must be used when implementing ECC.
The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into
the DDRI SDRAM array along with the data and is checked when the data is read. If the code is
incorrect, the MCU corrects the data (if possible) before reaching the initiator of the read. ECC
error scrubbing must be done with software. User-defined fault correction software is responsible
for scrubbing the memory array and handling double-bit errors.
Device function
OTG function
High-speed interface
DDRI 266 SDRAM
128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support
Only unbuffered DRAM support (No registered DRAM support)
Dedicated port for Intel XScale core to DDR SDRAM
Between 32 Mbyte and 1 Gbyte of 32-bit DDR SDRAM for low-cost solutions
Single-bit error correction, multi-bit detection support (ECC)
32-, 40-bit wide Memory Interfaces (non-ECC and ECC support)
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002

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