GWIXP455BAC Intel, GWIXP455BAC Datasheet - Page 35

• Manufacturer Part Number: GWIXP455BAC
• Manufacturer: Intel

Specifications of GWIXP455BAC

• Core Operating Frequency: 400MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

3.2.2
3.2.3
Intel
Document Number:
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IXP45X and Intel
The MAC pipe has six to nine stages:
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or
MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to successfully
predict the outcome of branch instructions. The branch target buffer provides such a means.
Branch Target Buffer
Each entry of the 128-entry Branch Target Buffer (BTB) contains the address of a branch
instruction, the target address associated with the branch instruction, and a previous history of the
branch being taken or not taken. The history is recorded as one of four states:
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or weakly
taken, the instruction at the branch target address is fetched. When its history is strongly or weakly
not-taken, the next sequential instruction is fetched. In either case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is taken. This
data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when
present).
Successfully predicted branches avoid any branch-latency penalties in the super pipeline.
Unsuccessfully predicted branches result in a four-to-five-cycle, branch-latency penalty in the
super pipeline.
Instruction Memory Management Unit
For instruction pre-fetches, the Instruction Memory Management Unit (IMMU) controls logical-to-
physical address translation, memory access permissions, memory-domain identifications, and
attributes (governing operation of the instruction cache).
The IMMU contains a 32-entry, fully associative instruction-translation, look-aside buffer (ITLB)
that has a round-robin replacement policy. ITLB entries zero through 30 can be locked.
When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The
descriptor contains information for logical-to-physical address translation, memory-access
permissions, memory-domain identifications, and attributes governing operation of the I-cache.
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306261-002
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The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
. . . then finishes with the following MAC stages
MAC 1
MAC 2
MAC 3
MAC 4
Data Cache Writeback
Strongly taken
IXP46X Product Line of Network Processors Datasheet
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Weakly taken
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Weakly not taken
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Functional Overview
Strongly not taken
May 2005
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