GWIXP455BAC Intel, GWIXP455BAC Datasheet - Page 51

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GWIXP455BAC

Manufacturer Part Number
GWIXP455BAC
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP455BAC

Core Operating Frequency
400MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Package Information
Table 12.
May 2005
51
PCI_TRDY_N
PCI_IRDY_N
PCI_STOP_N
PCI_PERR_N
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
Name
processor, see
PCI Controller (Sheet 2 of 5)
Reset
Power
Table 1 on page
on
Z
Z
Z
Z
Reset
Z
Z
Z
Z
Table 10 on page
14.
Software
Enables
Normal
Reset
After
Until
VB
VB
VB
VB
Software
Enables
Normal
46.
After
VB
VB
VB
VB
®
IXP45X and Intel
Type
I/O
I/O
I/O
I/O
PCI Target Ready informs that the target of the PCI bus is ready to complete the current data phase
of a given transaction.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Initiator Ready informs the PCI bus that the initiator is ready to complete the transaction.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Stop indicates that the current target is requesting the current initiator to stop the current
transaction.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Parity Error asserted when a PCI parity error is detected — between the PCI_PAR and associated
information on the PCI_AD bus and PCI_CBE_N — during all PCI transactions, except for Special
Cycles. The agent receiving data will drive this signal.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
®
IXP46X Product Line of Network Processors. For details on feature support listed by
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
®
®
®
®
IXP45X and Intel
IXP45X and Intel
IXP45X and Intel
IXP45X and Intel
Document Number:
®
®
®
®
IXP46X Product Line of
IXP46X Product Line of
IXP46X Product Line of
IXP46X Product Line of
306261-002

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