PRIXP423BD Intel, PRIXP423BD Datasheet - Page 22

• Manufacturer Part Number: PRIXP423BD
• Manufacturer: Intel

Specifications of PRIXP423BD

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
Intel
Datasheet
22
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Internal Bus
The internal bus architecture of the IXP42X product line and IXC1100 control plane
processors is designed to allow parallel processing to occur and to isolate bus
utilization, based on particular traffic patterns. The bus is segmented into three major
buses: the North AHB, South AHB, and APB.
North AHB
The North AHB is a 133.32 MHz, 32-bit bus that can be mastered by the NPEs. The
targets of the North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB
bridge allows the NPEs to access the peripherals and internal targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted
predominately to the queue manager. Transfers to the AHB/AHB bridge may be
“posted,” when writing, or “split,” when reading.
When a transaction is “posted,” a master on the North AHB requests a write to a
peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write
request will be transferred from the master on the North AHB to the AHB/AHB bridge.
The AHB/AHB bridge will complete the write on the South AHB, when it can obtain
access to the peripheral on the South AHB. The North AHB is released to complete
another transaction.
When a transaction is “split,” a master on the North AHB requests a read of a peripheral
on the South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will
be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB
bridge will complete the read on the South AHB, when it can obtain access to the
peripheral on the South AHB.
Once the AHB/AHB bridge has obtained the read information from the peripheral on the
South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/
AHB bridge has the data for the master that requested the “split” transfer. The master
on the North AHB — that requested the split transfer — will arbitrate for the North AHB
and transfer the read data from the AHB/AHB bridge. The North AHB is released to
complete another transaction while the North AHB master — that requested the “split”
transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to
another master on the North AHB — enabling the North AHB to achieve maximum
efficiency. Transfers to the AHB/AHB bridge are considered to be small and infrequent,
relative to the traffic passed between the NPEs on the North AHB and the SDRAM.
South AHB
The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale
processor, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus
can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB
bridge.
Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the
APB.
APB Bus
The APB Bus is a 66.66 MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be
mastered by the AHB/APB bridge only. The targets of the APB bus can be:
Intel
®
IXP42X product line and IXC1100 control plane processors
Document Number: 252479-006US
August 2006
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