PRIXP423BD Intel, PRIXP423BD Datasheet - Page 26

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PRIXP423BD

Manufacturer Part Number
PRIXP423BD
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP423BD

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
2.1.13
2.1.14
2.1.15
2.2
Intel
Datasheet
26
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale
Intel 0.18-micron production semiconductor process technology. This process
technology enables the Intel XScale
power range, producing industry-leading mW/MIPS performance.
Intel XScale
Interrupt Controller
The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt
sources to allow an extension of the Intel XScale
sources. These sources can originate from some external GPIO pins or internal
peripheral interfaces.
The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled.
The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining
interrupts are prioritized in ascending order. For example, Interrupt 8 has a higher
priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.
Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal
timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task
scheduling and prevent software lock-ups. The device has four 32-bit counters:
AHB Queue Manager
The AHB Queue Manager (AQM) provides queue functionality for various internal
blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale
processor. The AHB interface is used for configuration of the AQM and provides access
to queues, queue status and SRAM. Individual queue status for queues 0-31 is
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale
Intel XScale
The Intel XScale technology is compliant with the ARM
architecture (ISA). The Intel XScale
• Seven/eight-stage super-pipeline promotes high-speed, efficient processor
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch
• 32-entry instruction memory-management unit for logical-to-physical address
• 32-entry data-memory management unit for logical-to-physical address
• Watch-Dog Timer
performance
choices
translation, access permissions, I-cache attributes
translation, access permissions, D-cache attributes
®
processor features include:
®
Processor
®
processor (or any other AHB bus master), a Flag Bus interface,
• Timestamp Timer
Intel
®
®
®
IXP42X product line and IXC1100 control plane processors
processor, shown in
processor to operate over a wide speed and
®
processor FIQ and IRQ interrupt
*
• Two general-purpose
Version 5TE instruction-set
Figure
timers
Document Number: 252479-006US
6, is designed with
®
processor.
August 2006
®

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