PRIXP423BD Intel, PRIXP423BD Datasheet - Page 45

• Manufacturer Part Number: PRIXP423BD
• Manufacturer: Intel

Specifications of PRIXP423BD

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Intel
Table 14.
Table 15.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
UART Interfaces
USB Interface
RXDATA0
TXDATA0
CTS0_N
RTS0_N
RXDATA1
TXDATA1
CTS1_N
RTS1_N
†
††
USB_DPOS
USB_DNEG
†
Name
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
For a legend of the Type codes, see
Power
or Sys
Reset
Reset
H
H
H
H
Z
Z
Z
Z
Power
or Sys
Reset
Reset
Z
Z
Reset
VO/PE
VO/PE
Intel
VI/PE
VI/PE
Post
VO
VO
VI
VI
®
Reset
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Post
Z
Z
Type
O
O
O
O
I
I
I
I
†
Type
I/O
I/O
UART serial data input to High-Speed UART Pins.
Should be pulled high
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a reset operation. High-Speed Serial UART Pins.
UART CLEAR-TO-SEND input to High-Speed UART Pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
LOOP-mode operation holds this signal in its inactive state (logic 1).
High-Speed UART Pins.
UART serial data input.
Should be pulled high
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a Reset operation. Console UART Pins.
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
LOOP-mode operation holds this signal in its inactive state (logic 1).
Console UART Pins.
†
Table 5 on page
Table 5 on page
Positive signal of the differential USB receiver/driver.
Negative signal of the differential USB receiver/driver.
33.
33.
††
††
through a 10-KΩ resistor when not being
through a 10-KΩ resistor when not being
Description
Description
Datasheet
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