GWIXP425ABDT Intel, GWIXP425ABDT Datasheet - Page 43

• Manufacturer Part Number: GWIXP425ABDT
• Manufacturer: Intel

Specifications of GWIXP425ABDT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Functional Signal Descriptions
Table 14.
Table 15.
June 2007
43
UART Interfaces (Sheet 2 of 2)
USB Interface
RTS0_N
RXDATA1
TXDATA1
CTS1_N
RTS1_N
†
††
USB_DPOS
USB_DNEG
†
Name
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
For a legend of the Type codes, see
Power
or Sys
Reset
Reset
H
H
H
Z
Z
Power
or Sys
Reset
Reset
Z
Z
Reset
VO/PE
VO/PE
VI/PE
Post
VO
VI
Reset
Post
Z
Z
Type
O
O
O
I
I
†
Type
I/O
I/O
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is
ready to exchange data. A reset sets the request to send signal to logic 1.
LOOP-mode operation holds this signal in its inactive state (logic 1). High-Speed UART Pins.
UART serial data input.
Should be pulled high
UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. Console UART
Pins.
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is
ready to exchange data. A reset sets the request to send signal to logic 1.
LOOP-mode operation holds this signal in its inactive state (logic 1). Console UART Pins.
†
Table 5 on page
Table 5 on page
Positive signal of the differential USB receiver/driver.
Negative signal of the differential USB receiver/driver.
30.
30.
††
through a 10-KΩ resistor when not being utilized in the system.
Intel
®
IXP45X and Intel
Description
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US