PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 29

• Manufacturer Part Number: PRIXP423ABD
• Manufacturer: Intel

Specifications of PRIXP423ABD

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Datasheet—Intel
2.2.9
2.2.10
2.2.11
June 2007
Document Number:
Write Buffer (WB)
The write buffer (WB) holds data for storage to memory until the bus controller can act
on it. The WB is eight entries deep, where each entry holds 16 bytes. The WB is
constantly enabled and accepts data from the Intel XScale
mini-data cache.
Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled.
When coalescing is disabled, stores to memory occur in program order regardless of
the attribute bits within the descriptors located in the DTLB. When coalescing is
enabled, the attribute bits within the descriptors located in the DTLB are examined to
determine when coalescing is enabled for the destination region of memory. When
coalescing is enabled in both CP15, R1 and the DTLB, data entering the WB can
coalesce with any of the eight entries (16 bytes) and be stored to the destination
memory region, but possibly out of program order.
Stores to a memory region specified to be non-cacheable and non-bufferable by the
attribute bits within the descriptors located in the DTLB causes the processor to stall
until the store completes. A coprocessor register can specify draining of the write
buffer.
Multiply-Accumulate Coprocessor (CP0)
For efficient processing of high-quality, media-and-signal-processing algorithms, CP0
provides 40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD), and 32 x 32 signed
multiplies. Special MAR and MRA instructions are implemented to move the 40-bit
accumulator to two Intel XScale
Intel XScale
accumulator can be stored or loaded to or from D-cache, mini-data cache, or memory
using two STC or LDC instructions.
The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/
low, high/low, or low/high 16 bits of a 32-bit Intel XScale
(multiplier) and another 32-bit Intel XScale
to produce a full, 32-bit product that is sign-extended to 40 bits and added to the
40-bit accumulator.
Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and
low/low 16-bits of a packed 32-bit, Intel XScale
and another packed 32-bit, Intel XScale
produce two 16-bits products that are both sign-extended to 40 bits and added to the
40-bit accumulator.
The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, Intel XScale
processor general register (multiplier) and another 32-bit, Intel XScale
general register (multiplicand) to produce a 64-bit product where the 40 LSBs are
added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32 multiply-
accumulate instructions complete in a single cycle.
Performance Monitoring Unit (PMU)
The performance monitoring unit contains two 32-bit, event counters and one 32-bit,
clock counter. The event counters can be programmed to monitor I-cache hit rate, data
caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and
instruction execution count.
®
252479-007US
IXP42X product line and IXC1100 control plane processors
®
processor general registers to the 40-bit accumulator (MRA). The 40-bit
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
processor general registers (MAR) and move two
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processor general register (multiplicand) to
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processor general register (multiplicand)
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processor general register (multiplier)
®
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processor general register
processor, D-cache, or
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processor
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Datasheet
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