PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 30
Manufacturer Part Number
Specifications of PRIXP423ABD
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
code can then restart program execution.
The debug unit has two hardware-instruction, break point registers; two hardware,
data-breakpoint registers; and a hardware, data-breakpoint control register. The
second data-breakpoint register can be alternatively used as a mask register for the
first data-breakpoint register.
A 256-entry trace buffer provides the ability to capture control flow messages or
addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the
JTAG port to the mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction
cache to hold a debug handler).
the particular enabled interface is not being used in the application. These external
resistor requirements are only needed if the particular model of Intel
Disabled features, within the IXP42X product line and IXC1100 control plane
processors, do not require external resistors as the processor will have internal pull-up
or pull-down resistors enabled as part of the disabled interface.
section of the document.
To determine which interfaces are not enabled within the IXP42X product line and
IXC1100 control plane processors, see
The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1
JTAG port consists of a test access port (TAP) controller, boundary-scan register,
instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.
The debug unit — when used with debugger application code running on a host system
outside of the Intel XScale
exception to stop program execution and redirect execution to a debug-handling
Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint,
external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once
execution has stopped, the debugger application code can examine or modify the Intel
Functional Signal Descriptions
Listed in the signal definition tables — starting at
line and IXC1100 control plane processors has the particular interface enabled and the
interface is not required in the application.
All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V
Signal Type Definitions (Sheet 1 of 2)
presents the legend for interpreting the Type field in the other tables in this
processor, to be debugged. It allows the debugger application code or a debug
processor’s state, coprocessor state, or memory. The debugger application
— are pull-up an pull-down resistor recommendations that are required when
Input pin only
Output pin only
Pin can be either an input or output
Open Drain pin
IXP42X product line and IXC1100 control plane processors—Datasheet
processor — allows a program, running on the Intel
Table 3 on page
Table 7, “SDRAM Interface” on