PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 33
Manufacturer Part Number
Specifications of PRIXP423ABD
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
Functional Signal Descriptions
For a legend of the Type codes, see
Table 5 on page
SDRAM Address: A0-A12 signals are output during the READ/WRITE commands and ACTIVE commands to
select a location in memory to act upon.
SDRAM Data: Bidirectional data bus used to transfer data to and from the SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the rising edge of SDM_CLKOUT. All output signals are
driven with respect to the rising edge of SDM_CLKOUT.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the current command is attempting to access.
SDRAM Row Address strobe/select (active low): Along with SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDRAM Column Address strobe/select (active low): Along with SDM_RAS_N, SDM_WE_N, and SDM_CS_N
signals determines the current command to be executed.
SDRAM Chip select (active low): CS# enables the command decoder in the external SDRAM when logic low and
disables the command decoder in the external SDRAM when logic high.
SDRAM Write enable (active low): Along with SDM_CAS_N, SDM_RAS_N, and SDM_CS_N signals determines
the current command to be executed.
SDRAM Clock Enable: CKE is driving high to activate the clock to an external SDRAM and driven low to de-
activate the CLK to an external SDRAM.
SDRAM Data bus mask: DQM is used to byte select data during read/write access to an external SDRAM.
IXP45X and Intel
IXP46X Product Line of Network Processors Datasheet