PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 98
Manufacturer Part Number
Specifications of PRIXP423ABD
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
Timing tests were performed with a 70-pF capacitor to ground.
Multiplexed Mode Values
Pulse width of EX_ALE (ADDR is valid at the rising edge of
Valid address hold time after from falling edge of EX_ALE
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
Valid data after the rising edge of EX_WR_N
Valid chip select after the falling edge of EX_ALE
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
Time needed between successive accesses on expansion
IXP42X product line and IXC1100 control plane processors—Datasheet