NHIXP435AE Intel, NHIXP435AE Datasheet
NHIXP435AE
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NHIXP435AE Summary of contents
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... Intel IXP43X Product Line of Network Processors Specification Update December 2008 Order Number: 316847; Revision: 005US ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725 visiting Intel’s Web Site ...
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... EMRS Code Example................................................................................................. 23 Tables 1 Part Numbers for the Intel 2 Part Numbers for the Intel 3 Tested Devices that Pass on the Intel December 2008 Order Number: 316847; Revision: 005US Technology Errata..................................................................... 7 ® IXP43X Product Line of Network Processors.......................... 10 ® IXP435 Multi-Service Residential Gateway Reference Platform 10 ® ...
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... Added • Added September 2007 002 Added Non-Intel XScale® Technology Errata 19 and 20 under Initial release of the document — The first specification update combining errata for the Intel April 2007 001 IXP43X Product Line of Network Processors ® Intel IXP43X Product Line of Network Processors ...
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... Line Application Note 1.2 Nomenclature Errata are design defects or errors. These may cause the behavior of Intel Product Line of Network Processors’ to deviate from the published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. ...
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... The following tables indicate the errata, specification changes, specification clarifications, or documentation changes that apply to the Intel of Network Processors. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. ...
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... Ethernet Control Protocol Frames Transmit-Defer Status Bit 11 No Fix Error PCI Doorbell Register Lock-up Condition When Using Two 11 No Fix Products Together that have Intel® IXP4XX Product Line of Network Processors Intel XScale® Processor Non-Branch Instruction in Vector 12 No Fix Table 12 ...
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... Intel XScale Steppings ® ® Intel Intel IXP43X IXP43X Errata No. Product Product Line of Line of Network Network Processors Processors 2.4 Specification Changes Steppings ® ® Intel Intel IXP43X IXP43X Errata Product Product No. Line of Line of Network Network Processors Processors ® Intel IXP43X Product Line of Network Processors ...
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... Commercial / Extended Temperature, Lead-Free / Compliant with Standard for Restriction on the Use of Hazardous Substances (RoHS) i Pin # 1 Notes: 1. Part Number field — For different part numbers of the Intel ® 2. Package ball counts — Intel IXP43X Product Line of Network Processors has a ball count of 460. 3. ...
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... IXP435 Multi-Service Residential Gateway Reference Platform ® Intel IXP43X Product Line of Network Processors Specification Update 10 ® IXP43X Product Line of Network Processors Speed Stepping Part Number (MHz) A1 667 NHIXP435AE A1 667 NHIXP435AET A1 533 NHIXP435AD A1 533 NHIXP435ADT A1 400 NHIXP435AC A1 400 NHIXP435ACT A1 533 NHIXP433AD A1 400 ...
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... No Fix. 4. PCI Doorbell Register Lock-up Condition When Using Two Products Together that have Intel Problem possible that the PCI bus can get in a locked condition when multiple products using the IXP4XX product line processors are connected in a system and these systems are using the PCI doorbell registers of the IXP4XX product line processors ...
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... Workaround: The Intel IXP43X Product Line of Network Processors has an Ethernet coprocessor that is configured by the Intel indicate length error on received frames only when stripping of pad bytes from the received frame is enabled. Implication: Length errors on received frames when pad stripping (Receive Control 1 Register, bit-1) is disabled will not be indicated to the NPE software when it reads the Receive status ...
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... Problem: The PADC1, PADC0, APDC1, and APDC0 complete bits in the PCI_DMACTRL register will not be cleared under certain conditions when the Intel XScale write-1-to-clear (W1C) to the appropriate bit. If another PCI DMA transfer is initiated after the clear to the PCI_DMACTRL register, an indication of complete will occur before the DMA transfer has been finished (because the complete bit may not have been cleared) ...
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... If the UART is operating in non-FIFO mode, there is a possibility of falsely receiving an Overrun Error under certain conditions even though an overrun did not occur. Implication: An erroneous interrupt to the Intel XScale processor may occur indicating that data was lost in the UART. Workaround: Using the UART in FIFO mode or in non-FIFO mode, the data should be rejected and resent. ® ...
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... GPIO[0] has a weak pull-up to 3.3V, if the GPIO0 is configured as input. The weak pull-up will appear internally and propagate all the way to the interrupt status register, INTR_ST. It will interrupt only the Intel XScale processor via either IRQ or FIQ (INTR_EN bit 6) that corresponds to the enabled GPIO0. ...
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... As a result, unable to pass and obtain USB2.0 compliant logo. The IPD is the time between the end of one packet to the start of the subsequent packet. Table 3. Tested Devices that Pass on the Intel Processors Device Storage: USB2.0 Flash Disk Storage: USB2.0 Flash Disk Storage: USB2 ...
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... Non-Intel XScale Technology Errata Descriptions condition. In addition, the Ethernet NPE uses internal control state to prevent repetitive flushing of the MAC Rx Engine FIFO. Status: No Fix. 23. Incorrect Strapping Configuration during Bootup Problem: The EX_ADDR[23:0] has a strong pull-up resistor attached internally. During bootup, the strapping value will be read incorrectly when the EX_ADDR[23:0] is attached to 1K ohm pull-down resistor ...
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... Problem: A bus abort occurs on a code fetch while an instruction TLB or I-Cache lock Move to Coprocessor from Intel XScale processor Register (MCR) command is outstanding. The processor fails to abort and instead executes the instruction returned on the aborting transaction. Parity errors are not affected. The bus abort may be due to an abort pin assertion ...
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... When the two values are not equal, the desired register exists. The Intel XScale processor does not implement any CP15 ID code registers other than the Main ID register (opcode2 = 0b000) and the Cache Type register (opcode2 = 0b001) ...
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... Problem: The IEEE 1149.1 specification states that the effect of updating all parallel JTAG registers should be seen on the falling edge of TCK in the Update-DR state. The Intel XScale processor parallel JTAG registers require an extra TCK rising edge to make the update visible. Therefore, operations like hold-reset, JTAG break, and vector traps require either an extra TCK cycle by going to Run-Test-Idle or by cycling through the state machine again in order to trigger the expected hardware behavior ...
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... Intel XScale Technology Errata Descriptions this bug, the first instruction of such an FIQ handler may be executed twice when it is not a branch instruction. Workaround: When an NOP is placed at the beginning of the FIQ handler, the NOP executes twice and there is no incorrect behavior. When a branch instruction is placed at the beginning of the handler, it does not execute twice ...
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... Affected Docs:Intel IXP43X Product Line of Network Processors Datasheet Line of Network Processors Hardware Design Guidelines and Intel® IXDP435 Multi- Service Residential Gateway Reference Platform Schematics 2. Updates to Pull-Down Resistor Value on JTG_TRST_N Issue: The JTG_TRST_N has a strong pull-up resistor attached internally. A 100 ohm pull-down is required to override this pull-up resistor. ® ...
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... EMRS OCD Default r1, [r0, #IXP_DDR_DCALCSR] r1, =0x00000381 //set bits [9:7] and bit 0 for EMRS OCD Default r1, [r0, #IXP_DDR_DCALADDR] r1, =0x00000001 //set bit 0 only for exit r1, [r0, #IXP_DDR_DCALADDR] r2, [r0, #IXP_DDR_DCALADDR] //restore original DCALADDR value Intel ® IXP43X Product Line of Network Processors Specification Update 23 ...
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... DQ, CB, and DM read input valid time after DQS rising or T VA4 falling edges ® Affected Docs:Intel IXP43X Product Line of Network Processors Datasheet and Intel® IXP43X Product Line of Network Processors Hardware Design Guidelines. ® Intel IXP43X Product Line of Network Processors Specification Update 24 6 ...