IS42S16400-8TLI ISSI, Integrated Silicon Solution Inc, IS42S16400-8TLI Datasheet - Page 2

• Manufacturer Part Number: IS42S16400-8TLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400-8TLI

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS42S16400
PIN FUNCTIONS
2
11,13, 42, 44, 45,
47, 48, 50, 51, 53
2, 4, 5, 7, 8, 10,
6, 12, 46, 52
3, 9, 43, 49
28, 41, 54
1, 14, 27
23 to 26
29 to 34
Pin No.
22, 35
20, 21
15, 39
17
37
38
19
18
16
BA0, BA1
Symbol
A0-A11
LDQM,
GNDQ
I/O0 to
UDQM
I/O15
V
GND
CAS
CKE
RAS
CLK
V
CS
WE
CC
CC
Q
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
I/O Pin
Type
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the op-code during
a LOAD MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode. The CKE is an asynchronous
input.
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
The device remains in the previous state when CS is HIGH.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre-
sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
"Command Truth Table" item for details on device commands.
V
V
GNDQ is the output buffer ground.
GND is the device internal ground.
WE, in conjunction with RAS and CAS, forms the device command. See the
CC
CC
Command input is enabled when CS is LOW, and disabled with CS is HIGH.
Q is the output buffer power supply.
is the device internal power supply.
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION Rev. 00A
ISSI
06/07/00
®