PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 10

• Manufacturer Part Number: PCI-BOARD/S25
• Manufacturer: Altera

Specifications of PCI-BOARD/S25

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Stratix PCI Development Board Data Sheet
10
DDR SDRAM Memory
The Stratix PCI development board was tested with the DDR SDRAM
Memory Controller MegaCore function version 1.2.0. A 256-MByte DDR
SDRAM memory module is installed in the 200-pin SODIMM connector
(J10) and connects to banks 3 and 4 of the I/O Stratix device.
Designers can use other memory modules provided they meet the
following requirements:
Flash Memory
The flash memory (U3) on the board connects to the Stratix device and the
MAX configuration controller. The flash memory is an Advanced Micro
Devices AM29DL640D 64-Mbit DL-family boot-block device that
connects to the Stratix device and the MAX configuration controller using
LVTTL signals.
The flash memory capacity is 8 MBytes (67,108,864 bits). The flash
memory contains one factory-programmed Stratix configuration image
and the remaining space can be used to store user-defined Stratix
configuration images and general-purpose user data such as Nios boot
code. The MAX controller design controls the partitioning and function of
the flash memory device.
of the flash memory device as shipped from the factory.
The flash memory can operate in either 8- or 16-bit modes. A signal that is
driven by the MAX configuration controller selects the mode in which the
flash memory device runs. The default MAX configuration controller
shipped with the board sets the flash memory device to operate in 8-bit
mode.
When the MAX configuration controller is not configuring the Stratix
device, it releases control of the flash memory to the Stratix device, which
can then perform write and read operations on the flash memory.
Reading, erasing, and writing to the flash memory requires strict
adherence to the required timing of the flash memory device. For
example, the flash memory has a read access time of 90 ns and flash write
operations (erase or program) take microseconds or longer to complete.
Therefore, the designer must monitor the flash memory status register for
proper operation. You can review the MAX configuration controller and
PCI-to-DDR SDRAM reference designs for sample Register Transfer
Language (RTL) source code that demonstrates typical flash memory
control operations.
200-pin SODIMM DDR SDRAM
64 bits (non-ECC) or 72 bits (ECC)
Table 7 on page 11
shows the actual portioning
Altera Corporation