MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 188
MT41J256M8DA-125:H
Manufacturer Part Number
MT41J256M8DA-125:H
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8DA-125H.pdf
(210 pages)
Specifications of MT41J256M8DA-125:H
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Figure 107: RESET Sequence
All voltage
supplies valid
and stable
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command
Address
BA[2:0]
RESET#
ODT
DQS
System RESET
CK#
CKE
A10
(warm boot)
DM
DQ
R
CK
TT
t IOZ = 20ns
T = 100ns (MIN)
MAX (10ns, 5 t CK)
T = 10ns (MIN)
High-Z
High-Z
High-Z
T (MIN) =
Note:
T = 500µs (MIN)
Stable and
valid clock
1
1. The minimum time required is the larger of 10ns or 5 clocks.
t IS
t IS
NOP
T0
DRAM ready
for external
commands
t CL
t CK
t XPR
t CL
BA1 = H
BA0 = L
BA2 = L
Code
Code
MR2
T1
MRS
t MRD
BA0 = H
BA1 = H
BA2 = L
MR3
Code
Code
MRS
188
t MRD
DLL ENABLE
MR1 with
BA0 = H
BA1 = L
BA2 = L
Ta0
Code
Code
Valid
MRS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t MRD
2Gb: x4, x8, x16 DDR3 SDRAM
DLL RESET
MR0 with
BA0 = L
BA1 = L
BA2 = L
Code
Code
Tb0
Valid
MRS
t MOD
Indicates a break in
time scale
A10 = H
ZQ CAL
t DLLK
Tc0
Valid
ZQCL
© 2006 Micron Technology, Inc. All rights reserved.
RESET Operation
t ZQ
init
operation
Normal
Valid
Td0
Valid
Valid
Valid
Valid
Valid
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