MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 42

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MT41J256M8DA-125:H

Manufacturer Part Number
MT41J256M8DA-125:H
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT41J256M8DA-125:H

Lead Free Status / Rohs Status
Supplier Unconfirmed
Table 19: I
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
DD7
16
17
18
19
Measurement Loop (Continued)
3 × nFAW + 4 × nRRD + 1
3 × nFAW + 2 × nRRD
3 × nFAW + 3 × nRRD
3 × nFAW + 4 × nRRD
3 × nFAW + nRRD
Notes:
1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. AL = CL-1.
Electrical Specifications – I
D
Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed
1
0
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0
Repeat sub-loop 11, use BA[2:0] = 5
Repeat sub-loop 10, use BA[2:0] = 6
Repeat sub-loop 11, use BA[2:0] = 7
0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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DD
Specifications and Conditions
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© 2006 Micron Technology, Inc. All rights reserved.
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Definitions
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