PSD813F2VA-15MI STMicroelectronics, PSD813F2VA-15MI Datasheet - Page 71
PSD813F2VA-15MI
Manufacturer Part Number
PSD813F2VA-15MI
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-15MI.pdf
(109 pages)
Specifications of PSD813F2VA-15MI
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
52
Lead Free Status / Rohs Status
Compliant
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INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to ’1.’ The PSD
Configuration Register bits are set to ’0.’ The code,
configuration, and PLD logic are loaded using the
Table 35. JTAG Enable Register
Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is
used to enable the JTAG signals.
JTAG_Enable
X
X
X
X
X
X
X
0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
0
0
0
0
0
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Doc ID 10552 Rev 3
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
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