HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 13

• Manufacturer Part Number: HYB39S256800CTL-8
• Manufacturer: Infineon Technologies

Specifications of HYB39S256800CTL-8

• Lead Free Status / Rohs Status: Not Compliant

refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control
signals including the clock are disabled. Returning CKE to high enables the clock and initiates the
refresh exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
DQM Function
„high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay
(DQM Data Disable Latency t
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t
clocks).
Suspend Mode
the internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t
Power Down
must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can
enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the
receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tref) of the device. Exit from this mode is performed by taking CKE „high“. One clock delay
is required for power down mode entry and and exit.
Auto Precharge
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-
Precharge function is initiated. The SDRAM automatically enters the precharge operation a time
delay equal to t
Precharge Command
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last
data out to apply the precharge command.
INFINEON Technologies
There is also a separate precharge command available. When RAS and WE are low and CAS is
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes
DQM has two functions for data I/O read and write operations. During reads, when it turns to
In order to reduce standby power consumption, a power down mode is available. All banks
WR
(“write recovery time”) after the last data in.
DQZ
). It also provides a data mask function for writes. When DQM is
CSL
).
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HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
DQW
= zero
8.00