HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 19

• Manufacturer Part Number: HYB39S256800CTL-8
• Manufacturer: Infineon Technologies

Specifications of HYB39S256800CTL-8

• Lead Free Status / Rohs Status: Not Compliant

Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have V
3. If clock rising time is longer than 1 ns, a time (t
4. If tT is longer than 1 ns, a time (t
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
7. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
8. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK
INFINEON Technologies
transition time is meas ured between V
circuit shown in fig.1.Specified tac and toh parameters are measured with a 50 pF only, without any resistive
termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
as follows:
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
for operations at less or equal 83 MHz will be available.
CLOCK
INPUT
OUTPUT
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
t
SETUP
t
HOLD
t
LZ
t
AC
il
= 0.4 V and V
1.4 V
t
CL
T
-1) ns has to be added to this parameter.
t
t
OH
CH
t
T
ih
ih
t
t
AC
HZ
and V
= 2.4 V with the timing referenced to the 1.4 V crossover point. The
2.4 V
0.4 V
SPT03404
il
T
. All AC measurements assume t
/2 - 0.5) ns has to be added to this parameter.
1.4 V
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HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
fig.1
Measurement conditions for
I/O
T
tac and toh
=1ns with the AC output load
50 pF
8.00