HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 26

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HYB39S256800CTL-8

Manufacturer Part Number
HYB39S256800CTL-8
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of HYB39S256800CTL-8

Lead Free Status / Rohs Status
Not Compliant
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
INFINEON Technologies
(Burst Length = 4, CAS latency = 2, 3)
CLK
Command
DQ’s
t
t
(Burst Length = 4, CAS latency = 2, 3)
CLK
Command
CAS
latency = 2
CAS
latency = 3
CK2
CK3
, DQ’s
, DQ’s
T0
NOP
T0
NOP
Input data for the Write is ignored.
1 Clk Interval
Write A
T1
DIN A0
Write A
T1
1 Clk Interval
DIN A0
DIN A0
Write B
T2
DIN B0
Read B
T2
don’t care
don’t care
T3
DIN B1
NOP
T3
don’t care
NOP
26
T4
DIN B2
NOP
T4
DOUT B0
NOP
T5
DIN B3
NOP
T5
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
DOUT B0
DOUT B1
NOP
256-MBit Synchronous DRAM
HYB39S256400/800/160CT(L)
T6
NOP
T6
DOUT B2
DOUT B1
NOP
T7
NOP
T7
DOUT B3
DOUT B2
NOP
T8
NOP
T8
DOUT B3
NOP
SPT03791
SPT03719

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